IP Library Granted Patent US 9,469,523
Granted Patent B2
US 9,469,523 · App. 14/694,908 · Granted Oct 18, 2016

Microelectromechanical system devices having through substrate vias and methods for the fabrication thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,469,523
App. No.
14/694,908
Granted
Oct 18, 2016
Kind
B2
Abstract

Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

Claims (50)

1. A Microelectromechanical Systems (“MEMS”) device, comprising:

a substrate having a top surface and a bottom surface;

a backside conductor formed over the bottom surface of the substrate;

a filled Through-Substrate-Via (TSV) extending through the substrate and contacting the backside conductor;

a dielectric layer disposed over the top surface of the substrate;

a patterned transducer layer disposed over the dielectric layer and patterned to include a primary transducer structure;

a patterned interconnect layer located between the dielectric layer and the patterned transducer layer, the patterned interconnect layer separated from the primary transducer structure by an air gap and patterned to include an interconnect line in ohmic contact with the filled TSV; and

an electrically-conductive plug extending from the primary transducer structure, through the air gap, and to the interconnect line such that an electrically-conductive path is provided from the primary transducer structure, through the electrically-conductive plug, through the interconnect line, through the filled TSV, and to the backside conductor;

wherein the electrically-conductive plug extends into the primary transducer structure.

2. The MEMS device of claim 1 further comprising a peripheral portion of a sacrificial layer bonding the patterned interconnect layer to the patterned transducer layer.

3. The MEMS device of claim 1 wherein the electrically-conductive plug is vertically aligned with the filled TSV, as taken along an axis orthogonal to the top surface of the substrate.

4. The MEMS device of claim 1 further comprising an opening in which the electrically-conductive plug is formed, the opening extending through at least the patterned transducer layer and having a width less than a width of the filled TSV.

5. The MEMS device of claim 1 wherein the primary transducer structure comprises an anchor region, and wherein the electrically-conductive plug comprises a neck region joined to the anchor region.

6. The MEMS device of claim 1 further comprising:

a substrate wafer portion including the substrate, the filled TSV, the dielectric layer, and the patterned transducer layer; and

a transducer wafer portion including the patterned transducer layer.

7. The MEMS device of claim 6 wherein the substrate wafer portion is fusion bonded to the transducer wafer portion.

8. The MEMS device of claim 6 further comprising a MEMS cap bonded to the transducer wafer portion opposite the substrate wafer portion, the MEMS cap lacking interconnect features.

9. The MEMS device of claim 1 further comprising:

a backside dielectric layer formed on the bottom surface of the substrate; and

a backside bond pad formed on the backside dielectric layer and vertically offset relative to the filled TSV;

wherein the backside conductor comprises an interconnect line electrically coupling the backside bond pad to the filled TSV.

10. A Microelectromechanical Systems (“MEMS”) device, comprising:

a substrate wafer portion including a substrate having a top surface and a bottom surface;

a transducer wafer portion bonded to the substrate wafer portion, the transducer wafer portion comprising:

a patterned transducer layer; and

a primary transducer structure formed in the patterned transducer layer;

a backside conductor disposed over the bottom surface of the substrate;

an electrically-conductive plug formed through the primary transducer structure and extending toward the substrate; and

a filled Through-Substrate-Via (TSV) extending from the top surface to the bottom surface of the substrate, the primary transducer structure electrically coupled to the backside conductor through the electrically-conductive plug and the filled TSV.

11. The MEMS device of claim 10 wherein the substrate wafer portion further comprises a partially-removed sacrificial layer to which the patterned transducer layer is bonded.

12. The MEMS device of claim 11 wherein a central portion of the partially-removed sacrificial layer is removed such that the electrically-conductive plug is exposed within the MEMS device.

13. A Microelectromechanical Systems (“MEMS”) device, comprising:

a substrate having a top surface and a bottom surface;

a backside conductor formed over the bottom surface of the substrate;

a filled Through-Substrate-Via (TSV) extending through the substrate and contacting the backside conductor;

a dielectric layer disposed over the top surface of the substrate;

a patterned transducer layer disposed over the dielectric layer and patterned to include a primary transducer structure;

a patterned interconnect layer located between the dielectric layer and the patterned transducer layer, the patterned interconnect layer separated from the primary transducer structure by an air gap and patterned to include an interconnect line in ohmic contact with the filled TSV; and

an electrically-conductive plug extending from the primary transducer structure, through the air gap, and to the interconnect line such that an electrically-conductive path is provided from the primary transducer structure, through the electrically-conductive plug, through the interconnect line, through the filled TSV, and to the backside conductor;

wherein the electrically-conductive plug and the filled TSV comprise separately-formed structures having different widths.

14. The MES device of claim 13 further comprising a peripheral portion of a sacrificial layer bonding the patterned interconnect layer to the patterned transducer layer.

15. The MEMS device of claim 13 wherein the electrically-conductive plug is vertically aligned with the filled TSV, as taken along an axis orthogonal to the top surface of the substrate.

16. The MEMS device of claim 13 further comprising an opening in which the electrically-conductive plug is formed, the opening extending through at least the patterned transducer layer and having a width less than a width of the filled TSV.

17. The MEMS device of claim 13 wherein the primary transducer structure comprises an anchor region, and wherein the electrically-conductive plug comprises a neck region joined to the anchor region.

18. The MEMS device of claim 13 further comprising:

a substrate wafer portion including the substrate, the filled TSV, the dielectric layer, and the patterned transducer layer; and

a transducer wafer portion including the patterned transducer layer.

19. The MEMS device of claim 18 wherein the substrate wafer portion is fusion bonded to the transducer wafer portion.

20. The MEMS device of claim 18 further comprising a MEMS cap bonded to the transducer wafer portion opposite the substrate wafer portion, the MEMS cap lacking interconnect features.

Assignments (15)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2026
From: NXP USA, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 075219/0798 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 20, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037565/0510 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 20, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037565/0527 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0859 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 036284/0105 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 036284/0363 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 6, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 036284/0339 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2015
From: LIU, LIANJUN
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 035484/0759 →