Back-side illuminated pixels with interconnect layers
An imaging pixel may be provided with an upper substrate layer, a lower substrate layer, a floating diffusion region in the upper substrate layer, and a photodiode in the upper substrate layer that is coupled to the floating diffusion region. The imaging pixel may also include a source follower transistor in the lower substrate layer and an interconnect layer in between the upper substrate layer and the lower substrate layer. The interconnect layer may couple the floating diffusion region directly to the source follower transistor. The imaging pixel may include a reset transistor in the upper substrate layer. The imaging pixel may include a metal layer in the lower substrate layer, a transfer transistor in the upper substrate layer, and an interconnect layer that couples the transfer transistor to the metal layer.
1. An imaging pixel comprising:
an upper substrate layer;
a lower substrate layer;
a floating diffusion region in the upper substrate layer;
a photodiode in the upper substrate layer that is coupled to the floating diffusion region;
a source follower transistor in the lower substrate layer;
a first metal layer that is directly coupled to the floating diffusion region, wherein the first metal layer is formed in the upper substrate layer;
a second metal layer that is directly coupled to the source follower transistor, wherein the second metal layer is formed in the lower substrate layer; and
an interconnect layer that is interposed between the upper substrate layer and the lower substrate layer, wherein the interconnect layer is directly coupled to the first metal layer in the upper substrate layer and the second metal layer in the lower substrate layer wherein the first metal layer, the interconnect layer, and the second metal layer electrically couple the floating diffusion region directly to the source follower transistor, and wherein the first metal layer, the interconnect layer, and the second metal layer electrically couple the floating diffusion region to the source follower transistor without an intervening additional floating diffusion region.
2. The imaging pixel defined in claim 1 , further comprising:
a reset transistor in the upper substrate layer.
3. The imaging pixel defined in claim 2 , further comprising:
a transfer transistor in the upper substrate layer.
4. The imaging pixel defined in claim 3 , further comprising:
a row select transistor in the lower substrate layer.
5. The imaging pixel defined in claim 1 , further comprising:
a reset transistor, wherein the interconnect layer is not directly coupled to the reset transistor.
6. The imaging pixel defined in claim 5 , wherein the reset transistor is formed in the upper substrate layer.
7. The imaging pixel defined in claim 1 , further comprising:
a transfer transistor in the upper substrate layer;
a metal layer in the lower substrate layer and
an additional interconnect layer that couples the transfer transistor to the metal layer.
8. The imaging pixel defined in claim 1 , wherein the interconnect layer comprises metal.
9. The imaging pixel defined in claim 1 , wherein the interconnect layer is positioned such that incoming photons are reflected off of the interconnect layer and towards the photodiode.
10. An imaging pixel comprising:
a first substrate layer;
a second substrate layer;
a floating diffusion region in the first substrate layer;
a photodiode in the first substrate layer that is coupled to the floating diffusion region;
a source follower transistor in the second substrate layer that is coupled to the floating diffusion region;
a bias voltage supply line in the first substrate layer; and
a reset transistor in the first substrate layer that is coupled between the bias voltage supply line and the floating diffusion region.
11. The imaging pixel defined in claim 10 , further comprising:
a row select transistor in the second substrate layer.
12. The imaging pixel defined in claim 11 , further comprising:
an interconnect layer in between the first substrate layer and the second substrate layer, wherein the interconnect layer couples the floating diffusion region directly to the source follower transistor.
13. The imaging pixel defined in claim 12 , further comprising:
a transfer transistor in the first substrate layer.
14. The imaging pixel defined in claim 13 , further comprising:
a metal layer in the second substrate layer; and
an additional interconnect layer that couples the transfer transistor to the metal layer.
15. The imaging pixel defined in claim 10 , wherein the first substrate layer is formed above and overlaps the second substrate layer.
16. An imaging pixel comprising:
an upper substrate layer;
a lower substrate layer formed separately from the upper substrate layer, wherein the upper substrate layer overlaps the lower substrate layer;
a floating diffusion region in the upper substrate layer;
a photodiode in the upper substrate layer that is coupled to the floating diffusion region, wherein the photodiode is the only photodiode included in the imaging pixel;
a source follower transistor in the lower substrate layer; and
an interconnect layer interposed between the upper substrate layer and the lower substrate layer, wherein the interconnect layer couples the floating diffusion region directly to the source follower transistor.
17. The imaging pixel defined in claim 16 , wherein the interconnect layer is positioned below the upper substrate layer and above the lower substrate layer.
18. The imaging pixel defined in claim 16 , further comprising:
a bias voltage supply line in the upper substrate layer; and
a reset transistor in the upper substrate layer that is coupled between the floating diffusion region and the bias voltage supply line.
19. The imaging pixel defined in claim 1 , wherein the photodiode is the only photodiode included in the imaging pixel.