Method to improve reliability of replacement gate device
A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
1. A method of fabricating a gate stack for a semiconductor device, said method comprising steps of:
after removal of a dummy gate, providing a replacement gate structure by performing steps of:
growing a high-k dielectric layer over an area vacated by the dummy gate;
depositing a thin metal layer over the high-k dielectric layer;
depositing a sacrificial layer over the thin metal layer;
performing a first rapid thermal anneal;
removing the sacrificial layer from the thin metal layer to expose an entirety of the thin metal layer directly over a channel region of the semiconductor device; and
depositing a metal layer of low resistivity metal directly on an entirety of the thin metal layer in the gate stack.
2. The method of claim 1 further comprising:
performing a second rapid thermal anneal after annealing the structure.
3. The method of claim 2 performing the second rapid thermal anneal comprises performing a millisecond anneal with a laser.
4. The method of claim 2 wherein performing the second rapid thermal anneal comprises performing a millisecond anneal with a flash lamp.
5. The method of claim 1 wherein performing the first rapid thermal anneal comprises annealing at a temperature between 800° C. and 1100° C.
6. The method of claim 5 wherein performing the first rapid thermal anneal further comprises spiking the temperature for a period of time up to five seconds.
7. The method of claim 6 wherein performing the first rapid thermal anneal comprises annealing the structure in ambient nitrogen.
8. The method of claim 1 wherein depositing the metal layer comprises:
depositing a work function metal; and
depositing a gap fill metal of low resistivity.
9. The method of claim 1 wherein depositing the sacrificial layer comprises depositing a layer of polycrystalline silicon.
10. The method of claim 1 wherein depositing the sacrificial layer comprises depositing a layer of amorphous silicon.
11. A method of fabricating a gate stack for a semiconductor device, said method comprising steps of:
after removal of a dummy gate, providing a replacement gate structure by performing steps of:
growing a high-k dielectric layer over an area vacated by the dummy gate;
depositing a thin metal layer over the high-k dielectric layer;
depositing a sacrificial layer over the thin metal layer;
performing a first rapid thermal anneal;
removing the sacrificial layer from the thin metal layer to expose an entirety of the thin metal layer directly over a channel region of the semiconductor device;
depositing a metal layer of low resistivity metal directly on an entirety of the thin metal layer in the gate stack; and
performing a second rapid thermal anneal after annealing the structure.
12. The method of claim 11 performing the second rapid thermal anneal comprises performing a millisecond anneal with a laser.
13. The method of claim 12 wherein performing the second rapid thermal anneal comprises performing a millisecond anneal with a flash lamp.
14. The method of claim 11 wherein performing the first rapid thermal anneal comprises annealing at a temperature between 800° C. and 1100° C.
15. The method of claim 14 wherein performing the first rapid thermal anneal further comprises spiking the temperature for a period of time up to five seconds.
16. The method of claim 15 wherein performing the first rapid thermal anneal comprises annealing the structure in ambient nitrogen.
17. The method of claim 11 wherein depositing the metal layer comprises:
depositing a work function metal; and
depositing a gap fill metal of low resistivity.
18. The method of claim 11 wherein depositing the sacrificial layer comprises depositing a layer of polycrystalline silicon.
19. The method of claim 11 wherein depositing the sacrificial layer comprises depositing a layer of amorphous silicon.
20. The method of claim 11 , wherein removing the dummy gate comprises a selective etch.