IP Library Granted Patent US 11,289,381
Granted Patent B2
US 11,289,381 · App. 17/068,129 · Granted Mar 29, 2022

Methods of aligning a semiconductor wafer for singulation

Inventors: Michael J. Seddon (Gilbert, AZ); Takashi Noma (Ota, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/78H01L21/02057H01L21/304H01L21/32051H01L21/6836H01L22/10
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Quick Facts
Patent No.
US 11,289,381
App. No.
17/068,129
Granted
Mar 29, 2022
Kind
B2
Abstract

Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

Claims (33)

1. A method for aligning a semiconductor wafer for singulation, the method comprising:

providing a semiconductor wafer having a first side and a second side, the first side of the semiconductor wafer comprising a plurality of die, the semiconductor wafer comprising an edge ring around a perimeter of the semiconductor wafer on the second side of the semiconductor wafer, the semiconductor wafer further comprising a metal layer on the second side of the semiconductor wafer wherein the metal layer substantially covers the edge ring;

grinding the edge ring to create an edge exclusion area; and

aligning the semiconductor wafer with a saw using a camera facing the edge exclusion area on the second side of the semiconductor wafer using two or more alignment features comprised in the edge exclusion area.

2. The method of claim 1 , wherein the metal layer comprises copper having a thickness of 15 microns.

3. The method of claim 1 , further comprising singulating the plurality of die using one of sawing, lasering, or plasma etching.

4. The method of claim 1 , further comprising mounting the semiconductor wafer to a picking tape.

5. The method of claim 1 , wherein grinding further comprises washing debris from the semiconductor wafer.

6. The method of claim 1 , wherein the metal layer comprises one of gold, copper, nickel, or any combination thereof.

7. The method of claim 1 , wherein the camera is an infrared camera and the semiconductor wafer comprises silicon.

8. A method for aligning a semiconductor wafer for singulation, the method comprising:

providing a semiconductor wafer comprising a first side and a second side, the semiconductor wafer comprising an edge ring around a perimeter of the semiconductor wafer on the second side of the semiconductor wafer;

applying a metal coating to the second side of the semiconductor wafer, wherein the metal coating extends substantially over the edge ring;

creating an edge exclusion area through removal of the edge ring;

aligning the semiconductor wafer using two or more alignment features in the edge exclusion area using an infrared camera; and

monitoring a remaining thickness of the metal coating during singulation using laser ablation with the infrared camera.

9. The method of claim 8 , wherein the metal coating is applied through one of sputtering, evaporation, or plating.

10. The method of claim 8 , further comprising mounting the semiconductor wafer to a film frame.

11. The method of claim 8 , further comprising singulating a plurality of semiconductor die from the semiconductor wafer using one of sawing, lasering, or plasma etching.

12. The method of claim 8 , wherein the metal coating has a thickness of at least 15 microns.

13. The method of claim 8 , wherein removal of the edge ring comprises grinding and washing the semiconductor wafer.

14. The method of claim 8 , further comprising thinning the semiconductor wafer to form the edge ring.

15. A method for aligning a semiconductor wafer for singulation, the method comprising:

mounting a first side of a semiconductor wafer to a backgrinding tape, the semiconductor wafer comprising an edge ring around a perimeter of the semiconductor wafer on a second side of the semiconductor wafer;

applying a metal layer to the second side of the semiconductor wafer, wherein the metal layer extends substantially over the edge ring;

grinding the edge ring and removing the metal layer in a perimeter area of the semiconductor wafer;

aligning the semiconductor wafer for singulation using a camera and two or more alignment features in the perimeter area of the semiconductor wafer; and

adjusting one of a singulating perimeter or an alignment of the semiconductor wafer using the camera during singulation.

16. The method of claim 15 , wherein the metal layer is applied through one of sputtering, evaporation, and plating.

17. The method of claim 15 , further comprising singulating a plurality of die from the semiconductor wafer using a laser.

18. The method of claim 15 , wherein the metal layer comprises copper having a thickness of 15 microns.

19. The method of claim 15 , wherein the removing the edge ring through grinding further comprises washing debris from the semiconductor wafer.

20. The method of claim 15 , wherein the camera is an infrared camera and the semiconductor wafer is silicon.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2020
From: SEDDON, MICHAEL J.; NOMA, TAKASHI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054027/0376 →