IP Library Granted Patent US 11,756,830
Granted Patent B2
US 11,756,830 · App. 17/320,582 · Granted Sep 12, 2023

Jet ablation die singulation systems and related methods

Inventor: Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/78H01L21/3046H01L21/3065H01L21/561H01L23/3171
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Quick Facts
Patent No.
US 11,756,830
App. No.
17/320,582
Granted
Sep 12, 2023
Kind
B2
Abstract

Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.

Claims (21)

1. A method of singulating a plurality of semiconductor die, the method comprising:

forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate, the semiconductor substrate comprising a plurality of semiconductor die;

using the back metal layer as a mask layer, etching into the semiconductor substrate; and

jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die following etching into the semiconductor substrate.

2. The method of claim 1 , further comprising demounting the semiconductor substrate from a first tape and mounting the semiconductor substrate to a second tape.

3. The method of claim 2 , wherein demounting the semiconductor substrate from the first tape further comprises demounting after etching into the semiconductor substrate.

4. The method of claim 1 , further comprising mounting the semiconductor substrate to a first tape after etching into the semiconductor substrate.

5. The method of claim 1 , wherein jet ablating the layer of passivation material further comprises jet ablating from the second side of the semiconductor substrate.

6. The method of claim 1 , wherein jet ablating the layer of passivation material further comprises jet ablating from the first side of the semiconductor substrate.

7. The method of claim 1 , wherein etching into the semiconductor substrate comprises etching entirely through a thickness of the semiconductor substrate.

8. The method of claim 1 , wherein etching into the semiconductor substrate comprises etching substantially through a thickness of the semiconductor substrate.

9. The method of claim 8 , further comprising jet ablating a remaining portion of semiconductor substrate in the die street with the layer of passivation material coupled to the second side of the semiconductor substrate to singulate the plurality of semiconductor die following etching into the semiconductor substrate.

10. A method of singulating a plurality of semiconductor die, the method comprising:

forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate, the semiconductor substrate comprising a plurality of semiconductor die;

mounting the semiconductor substrate to a first tape;

using the back metal layer as a mask layer, etching into the semiconductor substrate; and

jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die following etching into the semiconductor substrate.

11. The method of claim 10 , further comprising demounting the semiconductor substrate from the first tape and mounting the semiconductor substrate to a second tape.

12. The method of claim 10 , wherein etching into the semiconductor substrate further comprises plasma etching.

13. The method of claim 10 , wherein a thickness of the semiconductor substrate is less than 50 microns.

14. The method of claim 10 , wherein the back metal comprises a thickness between 1 micron to 15 microns.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 057054, FRAME 0706 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064083/0001 →
SECURITY INTEREST Recorded Aug 2, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 057054/0706 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2021
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 056242/0831 →
Continuity (3)
Continuation 16807438 · Mar 3, 2020
Continuation 16136026 · Sep 19, 2018
Related Publication 20210272847A1 · Sep 2, 2021