IP Library Patent Application 17354096
Patent Application
App. No. 17/354,096

SEMICONDUCTOR DEVICE PACKAGE HAVING A BALL GRID ARRAY WITH MULTIPLE SOLDER BALL MATERIALS

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Quick Facts
Patent No.
US None
App. No.
17/354,096
Filed
Jun 22, 2021
Art Unit
2898
USPC
257/781
Abstract

A semiconductor device package includes a semiconductor device with a ball grid array having a first subset of solder balls composed of metallic solder, and a second subset of solder balls composed of a composite material that includes a polymer core surrounded by a solder layer. The solder balls of the second subset can have a lower elastic modulus than the solder balls of the first subset and resist cracking due to thermal stresses on the semiconductor device package. In one embodiment, at least a portion of the second subset of solder balls is located on the periphery of the ball grid array such that the first subset of solder balls may be surrounded, at least partially, by the second subset of solder balls.

Claims (30)

1 . A semiconductor device package, comprising:

a semiconductor device having a ball grid array disposed on a side of the semiconductor device, the ball grid array comprising:

a first subset of solder balls composed of a first material; and

a second subset of solder balls composed of a second material that is different than the first material.

2 . The semiconductor device package of claim 1 , wherein the first material is a metallic solder, and wherein the second material is a composite material comprising at least one polymer.

3 . The semiconductor device package of claim 2 , wherein the composite material includes a core comprising the at least one polymer and further comprises a solder layer surrounding the core.

4 . The semiconductor device package of claim 3 , wherein the solder layer of the second material has a melting temperature that is the same as the melting temperature of the metallic solder of the first material.

5 . The semiconductor device package of claim 2 , wherein the second material further comprises one or more inner layers disposed between the core and the solder layer, the one or more inner layers comprising one or more metallic layers having a melting temperature greater than the melting temperature of the solder layer.

6 . The semiconductor device package of claim 1 , wherein the first material has an elastic modulus that is greater than an elastic modulus of the second material.

7 . The semiconductor device package of claim 1 , wherein at least a portion of the second subset of solder balls are positioned at one or more corners of the ball grid array.

8 . The semiconductor device package of claim 7 , wherein a solder ball of the second subset of solder balls is positioned at each corner of the ball grid array.

9 . The semiconductor device package of claim 1 , wherein the ball grid array includes one or more peripheral rows and/or one or more peripheral columns that are composed entirely of solder balls of the second subset of solder balls.

10 . The semiconductor device package of claim 9 , wherein all of the solder balls of the second subset of solder balls are positioned in the one or more peripheral rows and/or the one or more peripheral columns of the ball grid array.

11 . The semiconductor device package of claim 1 , wherein each solder ball of the first subset is located between at least two solder balls of the second subset in a same column or row of the ball grid array.

12 . The semiconductor device package of claim 1 , wherein the first subset of solder balls is surrounded by the second subset of solder balls.

13 . The semiconductor device package of claim 1 , wherein at least a portion of the second subset of solder balls is electrically isolated from the semiconductor device.

14 . The semiconductor device package of claim 1 , further comprising a substrate coupled electrically and mechanically to the semiconductor device by the ball grid array.

15 . The semiconductor device package of claim 14 , wherein an underfill material is not present between the semiconductor device and the substrate.

16 . A ball grid array for connecting a semiconductor device to a substrate, the ball grid array comprising:

a first subset of solder balls composed entirely of a metallic solder; and

a second subset of solder balls comprising a polymer core, a solder layer surrounding the polymer core, and one or more metallic layers disposed between the polymer core and the solder layer,

at least a portion of the second subset of solder balls being located on a periphery of the ball grid array.

17 . A semiconductor device package, comprising:

substrate means for providing electrical interconnections;

integrated circuit means for outputting electrical signals to the substrate means;

first solder ball means disposed between the integrated circuit means and the substrate means for electrically coupling the integrated circuit means to the substrate means; and

second solder ball means disposed between the integrated circuit means and the substrate means for mechanically coupling the integrated circuit means to the substrate, the second solder ball means comprising a material of lower elastic modulus and/or higher tensile strength than the first solder ball means.

18 . The semiconductor device package of claim 17 , wherein the first solder ball means and the second solder ball means are arranged in an array, wherein the second solder ball means are positioned at least at one or more corners of the array.

19 . The semiconductor device package of claim 18 , wherein the first solder ball means is surrounded by the second solder ball means.

20 . The semiconductor device package of claim 17 , wherein at least a portion of the second solder ball means is electrically isolated from the integrated circuit means.

Assignments (8)
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2021
From: ZHANG, SIQI; LIU, YANGMING; WANG, WEI; RAI, PRADEEP; WANG, XU
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056708/0879 →