SiC MOSFET semiconductor packages and related methods
A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.
1 . A semiconductor package comprising:
one or more semiconductor die coupled between a baseframe and a clip, the baseframe comprising:
a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die; and
a source pad of the baseframe coupled with a source pad of the one or more semiconductor die;
wherein the source pad of the baseframe extends towards the gate pad of the one or more semiconductor die beyond a perimeter of the source pad of the one or more semiconductor die;
wherein the gate pad of the one or more semiconductor die extends beyond a perimeter of the gate pad of the baseframe; and
wherein the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.
2 . The package of claim 1 , further comprising an Ag sinter layer coupled between the one or more semiconductor die, the clip and the baseframe.
3 . The package of claim 1 , wherein the clip comprises a drain pad, the clip configured to couple with a drain pad of the one or more semiconductor die.
4 . The package of claim 1 , further comprising a mold compound enclosing a semiconductor die of the one or more semiconductor die on four sides of the semiconductor die.
5 . The package of claim 1 , further comprising a redistribution layer between the gate pad of the one or more semiconductor die and the gate pad of the baseframe.
6 . The package of claim 1 , further comprising a heat sink coupled directly to the one or more semiconductor die through a die adhesive material.
7 . The package of claim 1 , wherein the package is configured to provide electrical isolation between a termination ring of the one or more semiconductor die and the source pad of the one or more semiconductor die over an operating voltage range of 400 V to 1700 V.
8 . A semiconductor package comprising:
one or more semiconductor die coupled between a baseframe and a heat sink, the baseframe comprising:
a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die; and
a source pad of the baseframe coupled with a source pad of the one or more semiconductor die;
wherein a surface of the gate pad of the baseframe facing the one or more semiconductor die lies in the same plane as a surface of the source pad of the baseframe facing the one or more semiconductor die;
wherein the source pad of the baseframe extends towards the gate pad of the one or more semiconductor die beyond a perimeter of the source pad of the one or more semiconductor die; and
wherein the gate pad of the baseframe extends beyond a perimeter of a corresponding semiconductor die of the one or more semiconductor die;
wherein an entirety of the gate pad of the baseframe lies within a perimeter of a mold compound coupled to the baseframe.
9 . The package of claim 8 , further comprising an Ag sinter layer coupled between the one or more semiconductor die, the heat sink, and the baseframe.
10 . The package of claim 8 , wherein the heat sink comprises a drain pad, the heat sink configured to couple with a drain pad of the one or more semiconductor die.
11 . The package of claim 8 , further comprising a mold compound enclosing the one or more semiconductor die on four sides of each die of the one or more semiconductor die.
12 . The package of claim 8 , further comprising a redistribution layer between the gate pad of the one or more semiconductor die and the gate pad of the baseframe.
13 . A semiconductor package comprising:
a semiconductor die coupled between a baseframe and a clip;
a gate pad of the baseframe coupled with a gate pad of the semiconductor die; and
a source pad of the baseframe coupled with a source pad of the semiconductor die;
wherein a surface of the gate pad of the baseframe facing the semiconductor die lies in the same plane as a surface of the source pad of the baseframe facing the semiconductor die;
wherein the source pad of the baseframe extends towards the gate pad of the semiconductor die beyond a perimeter of the source pad of the semiconductor die;
wherein the gate pad of the semiconductor die extends beyond a perimeter of the gate pad of the baseframe; and
wherein the gate pad of the baseframe extends beyond a perimeter of the semiconductor die.
14 . The package of claim 13 , further comprising a second baseframe and a second clip, wherein a second die and a third die are coupled between the second baseframe and the second clip.
15 . The package of claim 13 , wherein the gate pad of the baseframe only partially covers the gate pad of the semiconductor die.
16 . The package of claim 13 , further comprising a mold compound enclosing four sides of the semiconductor die.
17 . The package of claim 13 , further comprising an Ag sinter layer coupled between the semiconductor die, the clip and the baseframe.
18 . The package of claim 13 , wherein the clip comprises a drain pad, the clip configured to couple with a drain pad of the semiconductor die.
19 . The package of claim 13 , further comprising a redistribution layer between the gate pad of the semiconductor die and the gate pad of the baseframe.
20 . The package of claim 13 , wherein the package is configured to provide electrical isolation between a termination ring of the semiconductor die and the source pad of the semiconductor die over an operating voltage range of 400 V to 1700 V.