Semiconductor device and method of forming hybrid TIM layers
A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.
1. A semiconductor device, comprising:
an electrical component;
a first thermal interface material (TIM) including a first compliant property disposed over a surface of the electrical component in a first pattern around a perimeter of the electrical component; and
a second TIM including a second compliant property greater than the first compliant property disposed over the surface of the electrical component within the first TIM in a second pattern different from the first pattern with no contact between the first TIM and second TIM.
2. The semiconductor device of claim 1 , further including an interconnect substrate, wherein the electrical component is disposed over the interconnect substrate.
3. The semiconductor device of claim 1 , further including a heat sink disposed over the first TIM and second TIM.
4. The semiconductor device of claim 1 , further including a third TIM disposed over the surface of the electrical component.
5. The semiconductor device of claim 1 , wherein the second pattern is selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
6. The semiconductor device of claim 1 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
7. A semiconductor device, comprising:
an electrical component;
a first thermal interface material (TIM) including a first compliant property disposed over a surface of the electrical component in a linear pattern around a perimeter of the electrical component; and
a second TIM including a second compliant property different from the first compliant property disposed over the surface of the electrical component in a non-linear pattern with no contact between the first TIM and second TIM.
8. The semiconductor device of claim 7 , further including an interconnect substrate, wherein the electrical component is disposed over the interconnect substrate.
9. The semiconductor device of claim 7 , further including a heat sink disposed over the first TIM and second TIM.
10. The semiconductor device of claim 7 , further including a third TIM disposed over the surface of the electrical component.
11. The semiconductor device of claim 7 , wherein the second pattern is selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
12. The semiconductor device of claim 7 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
13. The semiconductor device of claim 7 , further including:
a heat spreader disposed over the first TIM and second TIM;
a third TIM comprising the first compliant property disposed over a surface of the heat spreader;
a fourth TIM comprising the second compliant property disposed over the surface of the heat spreader within the first TIM; and
a heat sink disposed over the third TIM and fourth TIM.
14. A method of making a semiconductor device, comprising:
providing an electrical component;
disposing a first thermal interface material (TIM) including a first compliant property over a surface of the electrical component in a first pattern; and
disposing a second TIM including a second compliant property greater than the first compliant property over the surface of the electrical component within the first TIM in a second pattern separate from the first pattern with no contact between the first TIM and second TIM.
15. The method of claim 14 , further including:
providing an interconnect substrate; and
disposing the electrical component over the interconnect substrate.
16. The method of claim 14 , further including disposing a heat sink over the first TIM and second TIM.
17. The method of claim 14 , further including disposing a third TIM over the surface of the electrical component.
18. The method of claim 14 , wherein the second pattern is selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
19. The method of claim 14 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
20. A method of making a semiconductor device, comprising:
providing an electrical component;
disposing a first thermal interface material (TIM) including a first compliant property over a surface of the electrical component in a first pattern; and
disposing a second TIM including a second compliant property different from the first compliant property over the surface of the electrical component in a second pattern with no contact between the first TIM and second TIM.
21. The method of claim 20 , further including:
providing an interconnect substrate; and
disposing the electrical component over the interconnect substrate.
22. The method of claim 20 , further including disposing a heat sink over the first TIM and second TIM.
23. The method of claim 20 , further including disposing a third TIM over the surface of the electrical component.
24. The method of claim 20 , wherein the second pattern is selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
25. The method of claim 20 , further including:
disposing a heat spreader over the first TIM and second TIM;
disposing a third TIM comprising the first compliant property over a surface of the heat spreader;
disposing a fourth TIM comprising the second compliant property over the surface of the heat spreader within the first TIM; and
disposing a heat sink over the third TIM and fourth TIM.
26. A semiconductor device, comprising:
an electrical component;
a first thermal interface material (TIM) disposed over a surface of the electrical component in a first pattern; and
a second TIM disposed over the surface of the electrical component in a second pattern with no contact between the first TIM and second TIM.
27. The semiconductor device of claim 26 , wherein the first TIM includes a first compliant property and the second TIM includes a second compliant property different from the first compliant property.
28. The semiconductor device of claim 26 , further including an interconnect substrate, wherein the electrical component is disposed over the interconnect substrate.
29. The semiconductor device of claim 26 , further including a heat sink disposed over the first TIM and second TIM.
30. The semiconductor device of claim 26 , further including a third TIM disposed over the surface of the electrical component.
31. The semiconductor device of claim 26 , wherein the second pattern is selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
32. The semiconductor device of claim 26 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
33. The semiconductor device of claim 26 , further including:
a heat spreader disposed over the first TIM and second TIM;
a third TIM comprising the first compliant property disposed over a surface of the heat spreader;
a fourth TIM comprising the second compliant property disposed over the surface of the heat spreader within the first TIM; and
a heat sink disposed over the third TIM and fourth TIM.