Granted Patent B2

US 12,469,567 · App. 18/392,585 · Granted Nov 11, 2025

Inventors: Parth Amin (Fremont, CA); Xiangying Deng (Milpitas, CA); Nidhi Agrawal (San Jose, CA)

Assignee: Sandisk Technologies, Inc.

G11C16/26G11C5/063G11C16/0483G11C16/3481

Abstract

Claims (55)

1 . A memory apparatus, comprising:

memory cells configured to retain a threshold voltage corresponding to data states and disposed in memory holes coupled to bit lines and grouped into blocks; and

a control means coupled to the bit lines and configured to:

determine an amount of the memory cells of one of the blocks that are programmed based on an electrical current consumed by the memory apparatus during a fourth period of time of a read operation in which selected ones of the bit lines are ramped up to a bit line voltage,

adjust at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed, and

utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the data states in the read operation.

2 . The memory apparatus as set forth in claim 1 , wherein the memory cells are each connected to one of a plurality of word lines, the at least one read parameter includes an open block read pass voltage applied to unselected ones of the plurality of word lines connected to the memory cells in an erased state of the data states, the open block read pass voltage is selected to allow the memory cells connected to the unselected ones of the plurality of word lines connected to the memory cells in the erased state to conduct, and the control means is further configured to apply a read compare voltage for the one or more of the read levels to selected ones of the plurality of word lines while applying the open block read pass voltage to the unselected ones of the plurality of word lines connected to the memory cells in the erased state and while applying a normal read pass voltage to unselected ones of the plurality of word lines connected to the memory cells not in the erased state, the normal read pass voltage being different from the open block read pass voltage and selected to allow the memory cells connected to the unselected ones of the plurality of word lines connected to the memory cells not in the erased state to conduct.

3 . The memory apparatus as set forth in claim 2 , further including a delta open block read pass voltage parameter stored in the memory apparatus and defining an offset of the normal read pass voltage, and the control means is further configured to determine the open block read pass voltage as the normal read pass voltage plus the delta open block read pass voltage parameter.

4 . The memory apparatus as set forth in claim 1 , wherein the memory cells are each connected to one of a plurality of word lines, the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of the bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, the plurality of word lines includes a bottom word line vertically disposed adjacent a bottom of the stack and a top word line vertically disposed adjacent a top of the stack, the memory cells connected to the plurality of word lines are programmed in a programming order beginning with one of the bottom word line and the top word line and progressing vertically through the stack, and the control means is further configured to determine the amount of the memory cells of the one of the blocks that are programmed based on the electrical current consumed by the memory apparatus during the fourth period of time of the read operation while reading the memory cells connected to the one of the bottom word line and the top word line.

5 . The memory apparatus as set forth in claim 4 , further including a power circuit configured to measure the electrical current consumed by the memory apparatus, wherein the read operation includes a first period of time in which the plurality of word lines begin ramping up to a read pass voltage and a second period of time in which the bit line voltage applied to the bit lines is ramped up to a cell select voltage and the plurality of word lines reach the read pass voltage, and the control means is further configured to:

ramp up the plurality of word lines to the read pass voltage during the first period of time and the second period of time of the read operation;

lower the one of the bottom word line and the top word line and unselected ones of the drain-side select gate transistors to a steady state voltage;

ramp up the bit lines to the bit line voltage and a source line voltage applied to the source line to the cell select voltage;

using the power circuit, detect the electrical current consumed by the memory apparatus during the fourth period of time of the read operation;

decide an open block ratio according to the electrical current consumed by the memory apparatus detected by the power circuit, the open block ratio corresponding with the amount of the memory cells of the one of the blocks that are programmed; and

adjust at least one read parameter based on the open block ratio.

6 . The memory apparatus as set forth in claim 5 , wherein the control means is further configured to:

lower selected ones of the plurality of word lines to a read compare voltage for the one or more of the read levels while raising the one of the bottom word line and the top word line to the read pass voltage; and

continue the read operation using the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above the one or more of the read levels associated with each of the data states.

7 . The memory apparatus as set forth in claim 4 , wherein the control means is further configured to adjust at least one of the bit line voltage and a voltage of the source line to reduce the electrical current consumed during the fourth period of time of the read operation.

8 . A controller in communication with a memory apparatus including memory cells configured to retain a threshold voltage corresponding to data states and disposed in memory holes coupled to bit lines and grouped into blocks, the controller configured to:

instruct the memory apparatus to determine an amount of the memory cells of one of the blocks that are programmed based on an electrical current consumed by the memory apparatus during a fourth period of time of a read operation in which selected ones of the bit lines are ramped up to a bit line voltage;

adjust at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed; and

instruct the memory apparatus to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more of read levels associated with each of the data states in the read operation.

9 . The controller as set forth in claim 8 , wherein the memory cells are each connected to one of a plurality of word lines, the at least one read parameter includes an open block read pass voltage applied to unselected ones of the plurality of word lines connected to the memory cells in an erased state of the data states, the open block read pass voltage is selected to allow the memory cells connected to the unselected ones of the plurality of word lines connected to the memory cells in the erased state to conduct, and the controller is further configured to instruct the memory apparatus to apply a read compare voltage for the one or more of the read levels to selected ones of the plurality of word lines while applying the open block read pass voltage to the unselected ones of the plurality of word lines connected to the memory cells in the erased state and while applying a normal read pass voltage to unselected ones of the plurality of word lines connected to the memory cells not in the erased state, the normal read pass voltage being different from the open block read pass voltage and selected to allow the memory cells connected to the unselected ones of the plurality of word lines connected to the memory cells not in the erased state to conduct.

10 . The controller as set forth in claim 9 , wherein the memory apparatus further includes a delta open block read pass voltage parameter stored in the memory apparatus and defining an offset of the normal read pass voltage, and the controller is further configured to determine the open block read pass voltage as the normal read pass voltage plus the delta open block read pass voltage parameter.

11 . The controller as set forth in claim 8 , wherein the memory cells are each connected to one of a plurality of word lines, the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of the bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, the plurality of word lines includes a bottom word line vertically disposed adjacent a bottom of the stack and a top word line vertically disposed adjacent a top of the stack, the memory cells connected to the plurality of word lines are programmed in a programming order beginning with one of the bottom word line and the top word line and progressing vertically through the stack, and the controller is further configured to determine the amount of the memory cells of the one of the blocks that are programmed based on the electrical current consumed by the memory apparatus during the fourth period of time of the read operation while reading the memory cells connected to the one of the bottom word line and the top word line.

12 . The controller as set forth in claim 11 , wherein the memory apparatus further includes a power circuit configured to measure the electrical current consumed by the memory apparatus, the read operation includes a first period of time in which the plurality of word lines begin ramping up to a read pass voltage and a second period of time in which the bit line voltage applied to the bit lines is ramped up to a cell select voltage and the plurality of word lines reach the read pass voltage, and the controller is further configured to:

instruct the memory apparatus to ramp up the plurality of word lines to the read pass voltage during the first period of time and the second period of time of the read operation;

instruct the memory apparatus to lower the one of the bottom word line and the top word line and unselected ones of the drain-side select gate transistors to a steady state voltage;

instruct the memory apparatus to ramp up the bit lines to the bit line voltage and a source line voltage applied to the source line to the cell select voltage;

using the power circuit, detect the electrical current consumed by the memory apparatus during the fourth period of time of the read operation;

decide an open block ratio according to the electrical current consumed by the memory apparatus detected by the power circuit, the open block ratio corresponding with the amount of the memory cells of the one of the blocks that are programmed; and

adjust at least one read parameter based on the open block ratio.

13 . The controller as set forth in claim 12 , wherein the controller is further configured to:

instruct the memory apparatus to lower selected ones of the plurality of word lines to a read compare voltage for the one or more of the read levels while raising the one of the bottom word line and the top word line to the read pass voltage; and

instruct the memory apparatus to continue the read operation using the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above the one or more of the read levels associated with each of the data states.

14 . A method of operating a memory apparatus including memory cells configured to retain a threshold voltage corresponding to data states and disposed in memory holes coupled to bit lines and grouped into blocks, the method comprising the steps of:

determining an amount of the memory cells of one of the blocks that are programmed based on an electrical current consumed by the memory apparatus during a fourth period of time of a read operation in which selected ones of the bit lines are ramped up to a bit line voltage;

adjusting at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed; and

utilizing the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the data states in the read operation.

15 . The method as set forth in claim 14 , wherein the memory cells are each connected to one of a plurality of word lines, the at least one read parameter includes an open block read pass voltage applied to unselected ones of the plurality of word lines connected to the memory cells in an erased state of the data states, the open block read pass voltage is selected to allow the memory cells connected to the unselected ones of the plurality of word lines connected to the memory cells in the erased state to conduct, and the method further includes the step of applying a read compare voltage for the one or more of the read levels to selected ones of the plurality of word lines while applying the open block read pass voltage to the unselected ones of the plurality of word lines connected to the memory cells in the erased state and while applying a normal read pass voltage to unselected ones of the plurality of word lines connected to the memory cells not in the erased state, the normal read pass voltage being different from the open block read pass voltage and selected to allow the memory cells connected to the unselected ones of the plurality of word lines connected to the memory cells not in the erased state to conduct.

16 . The method as set forth in claim 15 , wherein the memory apparatus further includes a delta open block read pass voltage parameter stored in the memory apparatus and defining an offset of the normal read pass voltage, and the method further includes the step of determining the open block read pass voltage as the normal read pass voltage plus the delta open block read pass voltage parameter.

17 . The method as set forth in claim 14 , wherein the memory cells are each connected to one of a plurality of word lines, the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of the bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, the plurality of word lines includes a bottom word line vertically disposed adjacent a bottom of the stack and a top word line vertically disposed adjacent a top of the stack, the memory cells connected to the plurality of word lines are programmed in a programming order beginning with one of the bottom word line and the top word line and progressing vertically through the stack, and the method further includes the step of determining the amount of the memory cells of the one of the blocks that are programmed based on the electrical current consumed by the memory apparatus during the fourth period of time of the read operation while reading the memory cells connected to the one of the bottom word line and the top word line.

18 . The method as set forth in claim 17 , wherein the memory apparatus further includes a power circuit configured to measure the electrical current consumed by the memory apparatus, the read operation includes a first period of time in which the plurality of word lines begin ramping up to a read pass voltage and a second period of time in which the bit line voltage applied to the bit lines is ramped up to a cell select voltage and the plurality of word lines reach the read pass voltage, and the method further includes the steps of:

ramping up the plurality of word lines to the read pass voltage during the first period of time and the second period of time of the read operation;

lowering the one of the bottom word line and the top word line and unselected ones of the drain-side select gate transistors to a steady state voltage;

ramping up the bit lines to the bit line voltage and a source line voltage applied to the source line to the cell select voltage;

using the power circuit, detecting the electrical current consumed by the memory apparatus during the fourth period of time of the read operation;

deciding an open block ratio according to the electrical current consumed by the memory apparatus detected by the power circuit, the open block ratio corresponding with the amount of the memory cells of the one of the blocks that are programmed; and

adjusting at least one read parameter based on the open block ratio.

19 . The method as set forth in claim 18 , further including the steps of:

lowering selected ones of the plurality of word lines to a read compare voltage for the one or more of the read levels while raising the one of the bottom word line and the top word line to the read pass voltage; and

continuing the read operation using the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above the one or more of the read levels associated with each of the data states.

20 . The method as set forth in claim 17 , further including the step of adjusting at least one of the bit line voltage and a voltage of the source line to reduce the electrical current consumed during the fourth period of time of the read operation.

Assignments (8)

Continuity (1)

References Cited (24)