Power efficient unmatched data path architecture for non-volatile memory
To reduce power consumption and circuitry requirements, the following presents an “unmatched” data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input/output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process.
1 . A non-volatile memory device, comprising:
a control circuit configured to connect to an array of non-volatile memory cells, the control circuit comprising:
an internal data bus;
one or more data buffers; and
a plurality of input/output (IO) pads,
the control circuit configured to:
transfer data from the internal data bus to the one or more data buffers according to a plurality of first data transfer clocks;
transfer data from the one or more data buffers to the IO pads;
receive an input clock signal;
generate the plurality of data transfer clocks from the input clock signal, including selecting one of a plurality of values for an amount of offset between the input clock signal and the first data transfer clocks;
read data from the array of non-volatile memory cells; and
transfer the read data onto the internal data bus wherein waveforms of the read data on the internal data bus are multiple cycles of the of the input clock signal and selecting one of a plurality of values for the amount of offset between the input clock signal and first data transfer clocks comprises:
selecting no offset or an offset of one cycle of the input clock signal.
2 . The non-volatile memory device of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory device further comprising:
a memory die including the array of non-volatile memory cells, the memory die separate from and bonded to the control die.
3 . The non-volatile memory device of claim 1 , wherein the one or more data buffers are first in, first out (FIFO) data buffers.
4 . A non-volatile memory device comprising:
a control circuit configured to connect to an array of non-volatile memory cells, the control circuit comprising:
an internal data bus;
one or more data buffers;
a plurality of input/output (IO) pads; and
a plurality of multiplexers,
the control circuit configured to:
transfer data from the internal data bus to the one or more data buffers according to a plurality of first data transfer clocks;
transfer data from the one or more data buffers to the IO pads;
receive an input clock signal; and
generate the plurality of data transfer clocks from the input clock signal, including selecting one of a plurality of values for an amount of offset between the input clock signal and the first data transfer clocks,
wherein, to transfer data from the one or more data buffers to the IO pads, the control circuit is further configured to:
transfer data from the one or more data buffers to the multiplexers according to a second transfer clock;
transfer data from the multiplexers to the one or more data buffers to the IO pads; and
generate the second transfer clock from the input clock signal, including selecting one of a plurality of values for an amount of offset between the input clock signal and the second transfer clocks.
5 . The non-volatile memory device of claim 4 , wherein the plurality of values for the offset between the input clock signal and output are each less than a full cycle of the input clock signal.
6 . The non-volatile memory device of claim 4 , wherein the one or more data buffers are first in, first out (FIFO) data buffers.
7 . The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:
receive the input clock signal from a memory controller; and
transfer data from the IO pads to the memory controller.
8 . The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:
receive the selected one of a plurality of values for an amount of offset between the input clock signal and the first data transfer clocks.
9 . A memory system, comprising:
a memory device, comprising:
an array of non-volatile memory cells;
an internal data bus structure;
one or more data buffers;
a plurality of input/output (IO) pads; and
one or more control circuits connected to the array of non-volatile memory cells, the internal data bus structure, the one or more data buffers, and the plurality of IO pads, the one or more control circuits configured to:
read data from the array of non-volatile memory cells;
transfer the read data from the internal data bus to the one or more data buffers according to a plurality of first data transfer clocks;
transfer data from the one or more data buffers to the IO pads;
receive an input clock signal; and
generate the plurality of data transfer clocks from the input clock signal, including offsetting the first data transfer clocks from the input clock signal by an offset value; and
a memory controller, the memory controller configured to:
determine the offset value;
provide the determined offset value to the memory device;
read data from the array of non-volatile memory cells; and
transfer the read data onto the internal data bus wherein waveforms of the read data on the internal data bus are multiple cycles of the of the input clock signal and selecting one of a plurality of values for the amount of offset between the input clock signal and first data transfer clocks comprises:
selecting no offset or an offset of one cycle of the input clock signal.
10 . The memory system of claim 9 , wherein the memory controller is further configured to determine the offset value as part of a start-up routine.
11 . The memory system of claim 9 , wherein the one or more control circuits are formed on a control die and the array of memory cells are formed on a memory die separate from and bonded to the control die.
12 . The memory system of claim 9 , wherein the one or more data buffers are first in, first out (FIFO) data buffers.
13 . The memory system of claim 9 , wherein the one or more control circuits further comprise:
a plurality of multiplexers,
wherein, to transfer data from the one or more data buffers to the IO pads, the control circuit is further configured to:
transfer data from the one or more data buffers to the multiplexers according to a second transfer clock;
transfer data from the multiplexers to the one or more data buffers to the IO pads; and
generate the second transfer clock from the input clock signal, including selecting one of a plurality of values for an amount of offset between the input clock signal and the second transfer clocks.
14 . The memory system of claim 9 , wherein the plurality of values for the offset between the input clock signal and output are each less than a full cycle of the input clock signal.
15 . The memory system of claim 9 , wherein the one or more control circuits are further configured to:
receive the input clock signal from a memory controller; and
transfer data from the IO pads to the memory controller.
16 . The memory system of claim 9 , wherein the one or more control circuits are further configured to:
receive the selected one of a plurality of values for an amount of offset between the input clock signal and the first data transfer clocks.