Optimizing usage of multiple write paths on multi-tenant storage devices
Instead of ignoring workflow or priority of tenant, modify the write path according to the tenant behavior and system priority using the multi-tenant storage device. When writing information, the write path usually includes RAM memory where the host or device copies the data. The data is copied to the NVM storage element. The RAM memory may be either part of the storage controller (either SRAM or DRAM) or part of the host (like DRAM in HMB) that may be controlled by the storage controller. The RAM memories are used for different goals by the storage controller and optimizing the overall system performance (write/read) is a priority of the storage device. In multi-tenant architectures, the different tenants may have different priorities to have their requirements fulfilled. The tenant priority is passed by the host to the storage device through an interface and either be static or change dynamically during the device operation. Optimizing the write paths according to tenant workload and priority may be done by a module in the storage controller.
1. A multi-tenant data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is coupled to a first volatile memory and a second volatile memory distinct from the first volatile memory, wherein the controller is configured to:
direct data for a first write command to the first volatile memory;
determine that tenant behavior or system priority has changed; and
direct data for a second write command to the second volatile memory,
wherein the multi-tenant data storage device comprises a first tenant that is a read intensive tenant and a second tenant that is a write intensive tenant, and wherein the first write command and the second write command are from the second tenant.
2. The multi-tenant data storage device of claim 1 , wherein the first volatile memory is static random access memory (SRAM) and the second volatile memory is dynamic random access memory (DRAM).
3. The multi-tenant data storage device of claim 1 , wherein the controller is further configured to direct the data for the second write command to the first volatile memory after the direction to the second volatile memory.
4. The multi-tenant data storage device of claim 1 , wherein the second volatile memory is host memory buffer (HMB) and the first volatile memory is either:
static random access memory (SRAM); or
the second volatile memory is dynamic random access memory (DRAM).
5. The multi-tenant data storage device of claim 1 , wherein the determining comprises receiving priority change information.
6. The multi-tenant data storage device of claim 1 , wherein the determining comprises detecting a change in performance.
7. The multi-tenant data storage device of claim 1 , wherein the determining comprises determining a timer has expired.
8. The multi-tenant data storage device of claim 1 , wherein the determining comprises receiving a random write command from a first tenant.
9. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
route a first command through dynamic random access memory (DRAM), wherein the first command is from a first tenant;
route a second command through static random access memory (SRAM), wherein the second command is from a second tenant distinct from the first tenant;
change priority for one or more of the first tenant and the second tenant; and
route a third command through the SRAM, wherein the third command is from a third tenant distinct from the first tenant and the second tenant, wherein the first command is a write command, the second command is a read command, and the third command is a read command.
10. The data storage device of claim 9 , wherein the changing priority comprises changing the priority of the second tenant.
11. The data storage device of claim 10 , wherein the changing priority comprises changing routing of commands for the second tenant to route through the DRAM or host memory buffer (HMB).
12. The data storage device of claim 9 , wherein the changing priority is performed dynamically during device operation.
13. The data storage device of claim 9 , wherein the SRAM is divided between read operations for the second tenant and write operations for the third tenant.
14. The data storage device of claim 9 , wherein data routed through the DRAM is routed through the DRAM and then the SRAM and then to the memory device.
15. A multi-tenant data storage device, comprising:
means to store data; and
a controller coupled to the means to store data, wherein the controller is configured to:
route data associated with a first command through host memory buffer (HMB) and the means to store data;
determine that a priority has changed; and
route data associated with a second command through a static random access memory (SRAM) and the means to store data, wherein the data storage device is dynamic random access memory (DRAM) less,
wherein the multi-tenant data storage device comprises a first tenant that is a read intensive tenant and a second tenant that is a write intensive tenant, and wherein the first command and the second command are from the second tenant.
16. The multi-tenant data storage device of claim 15 , wherein the controller is configured to utilize a read look ahead (RLA) mechanism.
17. The multi-tenant data storage device of claim 16 , wherein the controller is configured to dedicate a first portion of the SRAM for write operations and a second portion for RLA operations.