Efficient sequential write gap processing
Gap processing is utilized to reorder out-of-order submissions on the normal submission queue. The controller is able to process logical block addresses (LBAs) that are received through the use of a normal NVMe submission queue (SQ) and a private SQ. The normal NVMe SQ will store the LBAs of commands that may arrive out of sequential order for processing. The private SQ is used to store an LBA that is received after a gap is detected. The private SQ is only read after a command is received on the normal SQ that contains the current First Gap LBA. If no entry in the private SQ is sequentially after the first gap LBA, no processing of the private SQ occurs. If the pulled LBA is next, then the LBA will be processed by the data storage device. If the pulled LBA is not next, then the zone gap processing will send the LBA back to the private SQ.
1 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
retrieve a first zone write command from a first submission queue (SQ) of a host device to write data to a zone, wherein the first zone write command comprises a first logical block address (LBA);
determine that the first zone write command would result in a LBA gap within the zone;
place the first zone write command in a second SQ, wherein the second SQ is stored external to the controller and configured to be private to the zone; and
retrieve a second zone write command from the first SQ, wherein the second zone write command comprises a second LBA.
2 . The data storage device of claim 1 , wherein the controller is further configured to:
execute the second zone write command; and
search the second SQ for zone write commands that can be processed without resulting in a LBA gap.
3 . The data storage device of claim 2 , wherein the controller is further configured to execute the first zone write command.
4 . The data storage device of claim 3 , wherein the controller is further configured to write the data for the zone to the memory device.
5 . The data storage device of claim 1 , wherein the controller is configured to assign a command index to the first zone write command, parse the first zone write command, and assign the zone to the first zone write command.
6 . The data storage device of claim 5 , wherein the controller is configured to perform zone gap processing after assigning the zone to the first zone write command.
7 . The data storage device of claim 6 , wherein zone gap processing comprises determining whether writing to the zone would result in the LBA gap.
8 . The data storage device of claim 1 , wherein the second SQ is a private SQ disposed in DDR memory.
9 . The data storage device of claim 1 , wherein the second SQ is searched after detecting that a zone write command fills the LBA gap.
10 . The data storage device of claim 1 , wherein the first SQ and the second SQ are stored in an external storage location distinct from the memory device.
11 . The data storage device of claim 10 , wherein the external storage location is a host memory buffer (HMB).
12 . The data storage device of claim 1 , wherein the controller is configured to:
indicate a gap variable of the first zone write command based on the determination, wherein the gap variable of the first zone write command identifies a LBA that fills the LBA gap; and
search the second SQ for a zone write command comprising a LBA that fills the LBA gap.
13 . The data storage device of claim 12 , wherein the controller is configured to continue indicating the gap variable of the first zone write command for write commands to write data to the zone received after the first zone write command until the LBA gap is filled.
14 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
retrieve a first zone write command having a first logical block address (LBA) from a first submission queue (SQ) of a host device to write data to a zone;
execute the first zone write command;
retrieve a second zone write command having a second LBA from a second SQ of a second host device to write to the zone;
determine that execution of the second zone write command would be out of order within the zone;
place the second zone write command in a third SQ, wherein the third SQ is distinct from the first and second SQ, stored external to the controller, and configured to be private to the zone;
retrieve a third zone write command having a third LBA;
execute the third zone write command;
retrieve the second zone write command; and
execute the second zone write command.
15 . The data storage device of claim 14 , wherein the controller is further configured to search the third SQ for additional zone write commands to execute.
16 . The data storage device of claim 15 , wherein the searching occurs after executing any zone write command.
17 . The data storage device of claim 14 , wherein a location of third SQ is further distinct from the memory device, and wherein the location is a host memory buffer (HMB).
18 . A data storage device, comprising:
means to store data; and
a controller coupled to the means to store data, wherein the controller is configured to:
determine whether a zone write command retrieved from a host device creates a logical block address (LBA) gap within a zone;
place the zone write command in a submission queue (SQ), wherein the SQ is stored in a host memory buffer (HMB) of the host device and configured to be private to the zone;
process other zone write commands;
search the SQ for zone write commands that can be executed without creating a LBA gap; and
execute zone write commands from the SQ that can be executed without creating a LBA gap.
19 . The data storage device of claim 18 , wherein processing other zone write commands comprises executing zone write commands that can be executed without creating a LBA gap and without being placed in the SQ.
20 . The data storage device of claim 18 , wherein the controller is configured to search the SQ after execution of any zone write command.