IP Library Granted Patent US 12,613,658
Granted Patent B2
US 12,613,658 · App. 18/443,975 · Granted Apr 28, 2026

Early read start time for random access SSDs

Inventors: Amir Segev (Meiter, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Sandisk Technologies, Inc.
G06F3/0659G06F3/0623G06F3/0673
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Quick Facts
Patent No.
US 12,613,658
App. No.
18/443,975
Granted
Apr 28, 2026
Kind
B2
Abstract

Instead of waiting for a write command to complete, a coherency table in a solid state drive (SSD) will expedite the read command start time. The coherency table allows a response to the write command will be sent to the host as soon as a write command is received. The coherency table will continue to process the write command through to the encryption/decryption (XTS) module and then over to the DRAM as normal. Once the read command reaches the coherency table, the command will be assessed for any issues. If there is an issue detected, then the coherency table will delay the read command until the previous write command reaches the DRAM (after going through the XTS module). Once the data from the write command reaches the DRAM the coherency table is cleared, and the read command is no longer delayed. The data can now be read from DRAM, decrypted in the XTS module and sent back to the host. Data is encrypted due to the write command before being sent to the DRAM. The data is decrypted due to the read command being read from the DRAM.

Claims (30)

1 . A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive a write command to write data to the memory device;

pass the write command to a coherency table;

send a notification to a host device responsive to passing the write command to the coherency table;

store an address for the write command in the coherency table;

receive a read command for data, wherein the read command is received from the host device responsive to the host device receiving the notification;

pass the read command to the coherency table; and

clear the address from the coherency table, wherein the clearing occurs after passing the read command to the coherency table.

2 . The data storage device of claim 1 , wherein the controller is configured to delay passing the read command from the coherency table to a data encryption/decryption module until after the clearing has occurred when data associated with the read command overlaps with data associated with the write command.

3 . The data storage device of claim 1 , wherein the controller is further configured to pass the read command from the coherency table to a data encryption/decryption module.

4 . The data storage device of claim 3 , wherein the controller is further configured to pass the data to the memory device, wherein the memory device is volatile memory.

5 . The data storage device of claim 4 , wherein the controller is further configured to inform the coherency table that the data has been written.

6 . The data storage device of claim 5 , wherein informing occurs after the passing the read command.

7 . The data storage device of claim 6 , wherein the data is returned from the memory device to the data encryption/decryption module prior to the informing.

8 . The data storage device of claim 4 , wherein passing the read command from the coherency table occurs prior to clearing the address from the coherency table when data associated with the read command is non-overlapping data relative to data associated with the write command.

9 . The data storage device of claim 1 , wherein the controller is further configured to detect an overlap of entries prior to passing the read command.

10 . The data storage device of claim 1 , wherein the clearing of the address from the coherency table occurs based writing the write command to the memory device.

11 . A data storage device, comprising:

means to store data; and

a controller coupled to the means to store data, wherein the controller is configured to:

receive a write command for data to be written to the means to store data, wherein executing the write command comprises:

adding an entry to a coherency table for the write command;

writing the data to the means to store data; and

clearing the entry from the coherency table after completing the writing of the data to the means to store data;

receive a read command for the data;

pass the read command to the coherency table prior to clearing the entry from the coherency table;

wait for there to be no collision at the coherency table; and

after the waiting, pass the read command from the coherency table to the means to store data after the clearing of the entry from the coherency table, wherein the controller is further configured to inform a host device that the entry has been made to the coherency table, wherein the read command is sent from a host device responsive to the informing.

Assignments (6)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0486 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069169/0572 →
PATENT COLLATERAL AGREEMENT (AR) Recorded May 15, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 067417/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2024
From: SEGEV, AMIR; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 067348/0651 →
Continuity (1)
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