Processing core including integrated high capacity high bandwidth storage memory
A processing core includes a multi-core processor integrated directly onto a high bandwidth, high-capacity non-volatile memory. The processor may for example be a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The non-volatile memory may comprise a CBA (CMOS bonded to array) memory tile having a single large NAND memory tile coupled together with a CMOS logic circuit tile. The integrated processor and CBA memory tile may be affixed to an interposer. The processing core may further include stacks of high bandwidth memory (HBM) semiconductor dies affixed to the interposer around one or more sides of the processor and CBA memory tile.
1. A processing core, comprising:
a signal-carrying medium;
a CMOS Bonded Array (CBA) memory tile physically and electrically coupled to the signal carrying medium, the memory tile comprising a first semiconductor tile bonded to a second semiconductor tile;
a processor mounted on the CBA memory tile, on a side of the CBA memory tile opposite the signal-carrying medium; and
one or more semiconductor memory dies mounted on the signal-carrying medium around one or more lateral sides of the CBA memory tile.
2. The processing core of claim 1 , wherein the first semiconductor tile comprises a plurality of memory cells.
3. The processing core of claim 2 , wherein the second semiconductor tile comprises a CMOS logic circuit for controlling access to the plurality of memory cells.
4. The processing core of claim 3 , wherein the processor comprises one or more processing cores.
5. The processing core of claim 3 , wherein the first semiconductor tile is bonded to the processor and the second semiconductor tile is coupled to the signal-carrying medium.
6. The processing core of claim 3 , wherein the second semiconductor tile is bonded to the processor and the first semiconductor tile is coupled to the signal-carrying medium.
7. The processing core of claim 1 , wherein the processor is one of a graphics processing unit and an artificial intelligence processor.
8. The processing core of claim 7 , wherein the CBA memory tile is the same length and width as the processor.
9. The processing core of claim 1 , further comprising a first set of electrical connections extending between the processor and the CBA memory tile.
10. The processing core of claim 9 , further comprising a second set of electrical connections extending between the processor and the one or more semiconductor memory dies through the CBA memory tile.
11. The processing core of claim 1 , wherein the one or more semiconductor memory dies comprise one or more stacks of high bandwidth memory.
12. The processing core of claim 1 , wherein the one or more semiconductor memory dies comprise one or more stacks of DRAM memory.
13. A processing core, comprising:
a signal-carrying medium;
one or more semiconductor memory dies physically and electrically coupled to the signal-carrying medium;
a CMOS bonded to array (CBA) memory tile physically and electrically coupled to the signal carrying medium, the CBA memory tile comprising:
a memory array tile comprising one or more first zones having memory arrays,
a CMOS logic circuit tile bonded to the memory array tile, the CMOS logic circuit tile comprising one or more second zones having CMOS logic circuits, the one or more second zones aligned with the one or more first zones,
one or more passthrough zones outside of the one or more first and second zones, the passthrough zones devoid of memory arrays and CMOS logic circuits; and
a processor mounted on the CBA memory tile, on a side of the CBA memory tile opposite the signal-carrying medium;
wherein the CBA memory tile further comprises:
a first set of electrical connections in the one or more first and second zones electrically coupling the CBA memory tile to the processor, and
a second set of electrical connections in the one or more passthrough zones electrically coupling the one or more semiconductor memory dies with the processor through the CBA memory tile.
14. The processing core of claim 13 , wherein the first set of electrical connections provide wide-word data transfer or faster between the CBA memory tile and the processor.
15. The processing core of claim 13 , wherein the second set of electrical connections comprise through silicon vias extending through the memory array tile and the CMOS logic circuit tile.
16. The processing core of claim 13 , wherein the second set of electrical connections further comprise power and ground signals coupled to the signal carrier medium.
17. The processing core of claim 13 , wherein the processor comprises multiple cores configured for parallel processing.
18. The processing core of claim 13 , wherein the CBA memory tile has the same footprint as the processor.
19. The processing core of claim 13 , wherein the one or more semiconductor memory dies comprise one of high bandwidth memory stacks of semiconductor dies and DRAM stacks of memory dies.