NVMe completion and interrupt
Instead of having uncertainty when waiting on completions, utilize unordered input output memory write (UIOMWr) to ensure the completions of the write. Using UIOMWr, the data storage device will write the competitions to a host dynamic random access memory (DRAM). When the device receives an approval of the completion, the device knows that the write to the host DRAM was successful. The approval will trigger the device to have the message signaled interrupts extended (MSIx) send an interrupt request (IRQ) to the host. The IRQ will pass through the PCIe and will be received by the host CPU. The host CPU will then process any pending completions in the host DRAM. An MSIx tag can be added to the completion (at the UIOMWr TLP level) that is assigned to multiple submission queues (SQ). When the MSIx tag is received by the host and device, the host and device will know what information needs to be pulled to avoid the need for translation later on.
1 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
send a nonvolatile memory express (NVMe) completion to a host device, wherein the NVMe completion has a tag, the tag being assigned to two or more completion queues of the host device;
send multiple NVMe completions to a same completion queue of the two or more completion queues utilizing multiple transaction layer packets (TLPs), wherein other TLPs of the multiple TLPs excluding a last TLP of the multiple TLPs do not use unordered input output memory write (UIOMWr);
receive a peripheral component interconnect express (PCle) completion from the host device, wherein the PCle completion has the tag; and
send an interrupt to the host device.
2 . The data storage device of claim 1 , wherein the tag is an indication of which message signaled interrupts extended (MSIx) or message signaled interrupt (MSI) or interrupt extended (INTx) to utilize.
3 . The data storage device of claim 1 , wherein the NVMe completion is for a first completion queue of the two or more completion queues and the PCle completion is for the first completion queue.
4 . The data storage device of claim 1 , wherein the controller uses UIOMWr to write the NVMe completion.
5 . The data storage device of claim 4 , wherein the controller is configured to send multiple UIOMWr completions with the same tag as the NVMe completion tag.
6 . The data storage device of claim 1 , wherein the controller is configured to increase a counter when sending the NVMe completion.
7 . The data storage device of claim 6 , wherein the controller is configured to decrease the counter when receiving the PCle completion.
8 . The data storage device of claim 7 , wherein the sending an interrupt is performed when the counter reaches 0 after being decreased to 0.
9 . The data storage device of claim 1 , wherein the interrupt is sent after multiple PCle completions have been received for a same completion queue.
10 . The data storage device of claim 1 , wherein the last TLP of the multiple TLPs uses UIOMWr.
11 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
send a first device completion notification to a completion queue of a host device;
send a second device completion notification to the completion queue of the host device, wherein the second device completion notification is sent prior to receiving a first host completion notification from the host device for the first device completion notification;
maintain a counter for completion notifications, wherein the counter is increased when sending each device completion notification, and wherein the counter is decreased when receiving each host completion notification; and
send an interrupt to the host device, wherein the interrupt is sent after receiving a second host completion notification from the host device for the second device completion notification, wherein the interrupt is sent when the counter is 0 after being decreased to 0.
12 . The data storage device of claim 11 , wherein the interrupt is an message signaled interrupts extended (MSIx) interrupt, a message signaled interrupt (MSI) interrupt, or an interrupt extended (INTx) interrupt.
13 . A data storage device, comprising:
means to store data; and
a controller coupled to the means to store data, wherein the controller is configured to:
send multiple transaction layer packets (TLPs) to a completion queue of a host device, the completion queue being assigned to a tag, wherein a last TLP of the multiple TLPs includes a uses unordered input output memory write (UIOMWr), and wherein other TLPs of the multiple TLPs excluding the last TLP do not include UIOMWr; and
send an interrupt to the host device after receiving an acknowledgement of the last TLP based on the last TLP having the UIOMWr.
14 . The data storage device of claim 13 , wherein interrupts are not sent to the host device after the other TLPs.
15 . The data storage device of claim 13 , wherein the controller is configured to send multiple UIOMWr completions with different tags.
16 . The data storage device of claim 13 , wherein the controller is configured to increase a counter when completions are sent, and decrease the counter when the controller determines that a host completion response has been received, and wherein a counter and a tag are different based on an message signaled interrupts extended (MSIx) vectors.
17 . The data storage device of claim 13 , wherein the controller is further configured to create a plurality of completion queues (CQs).