BONDING STRUCTURES FOR HIGH-DENSITY METAL-TO-METAL BONDING AND METHODS FOR FORMING THE SAME
A bonded assembly includes a first semiconductor die bonded to a second semiconductor die. The first semiconductor die includes first dielectric material layers located on first semiconductor devices, first metal interconnect structures embedded in the first dielectric material layers and electrically connected to the first semiconductor devices, a first bonding-level dielectric layer located on the first dielectric material layers and embedding a first electrically conductive bonding structure that is electrically connected to one of the first metal interconnect structures, and further embedding a first dummy electrically conductive bonding structure having a lesser vertical extent than the first electrically conductive bonding structure and electrically isolated from the first metal interconnect structures, and a first-type insulating spacer embedded in the first bonding-level dielectric layer and laterally surrounding the first electrically conductive bonding structure and vertically spaced from the second semiconductor die and from the first dielectric material layers.
1 . A bonded assembly, comprising:
a first semiconductor die; and
a second semiconductor die bonded to the first semiconductor die;
wherein the first semiconductor die comprises:
first dielectric material layers located on first semiconductor devices;
first metal interconnect structures embedded in the first dielectric material layers and electrically connected to the first semiconductor devices;
a first bonding-level dielectric layer located on the first dielectric material layers and embedding a first electrically conductive bonding structure that is electrically connected to one of the first metal interconnect structures, and further embedding a first dummy electrically conductive bonding structure having a lesser vertical extent than the first electrically conductive bonding structure and electrically isolated from the first metal interconnect structures; and
a first-type insulating spacer embedded in the first bonding-level dielectric layer and laterally surrounding the first electrically conductive bonding structure and vertically spaced from the second semiconductor die and from the first dielectric material layers.
2 . The bonded assembly of claim 1 , wherein:
the first-type insulating spacer is located entirely below and is vertically spaced from a first horizontal plane including a topmost surface of the first bonding-level dielectric layer; and
the first-type insulating spacer is located entirely above and is vertically spaced from a second horizontal plane including a bottommost surface of the first bonding-level dielectric layer.
3 . The bonded assembly of claim 1 , further comprising a second-type insulating spacer embedded in the first bonding-level dielectric layer and laterally surrounding the first dummy electrically conductive bonding structure.
4 . The bonded assembly of claim 3 , wherein:
the first-type insulating spacer comprises silicon carbonitride; and
the second-type insulating spacer comprises silicon carbonitride.
5 . The bonded assembly of claim 1 , wherein the first dummy electrically conductive bonding structure has a lesser vertical and lateral extent than the first electrically conductive bonding structure.
6 . The bonded assembly of claim 1 , wherein the first electrically conductive bonding structure has a first vertical cross-sectional profile including a first contoured sidewall comprising a first upper sidewall segment having a first upper taper angle relative to a vertical direction, a first lower sidewall segment having a first lower taper angle relative to the vertical direction, and a first connecting surface segment having a first connecting taper angle relative to the vertical direction, the first connecting taper angle being greater than the first upper taper angle and the first lower taper angle.
7 . The bonded assembly of claim 6 , wherein the first dummy electrically conductive bonding structure has a second vertical cross-sectional profile including a second contoured sidewall comprising a second upper sidewall segment having a second upper taper angle relative to the vertical direction, a second lower sidewall segment having a second lower taper angle relative to the vertical direction, and a second connecting surface segment having a second connecting taper angle relative to the vertical direction, the second connecting taper angle being greater than the second upper taper angle and the second lower taper angle.
8 . The bonded assembly of claim 7 , wherein:
the second upper taper angle is the same as the first upper taper angle; and
the second lower taper angle is the same as the first lower taper angle.
9 . The bonded assembly of claim 6 , wherein:
the first upper sidewall segment contacts the first bonding-level dielectric layer; and
a lower portion of the first lower sidewall segment contacts the first bonding-level dielectric layer.
10 . The bonded assembly of claim 9 , wherein:
an upper portion of the first lower sidewall segment contacts the first-type insulating spacer; and
the first connecting surface segment contacts the first-type insulating spacer.
11 . The bonded assembly of claim 1 , wherein the second semiconductor die comprises:
second metal interconnect structures embedded in second dielectric material layers; and
a second bonding-level dielectric layer embedding a second electrically conductive bonding structure that is electrically connected to a respective one of the second metal interconnect structures and bonded to the first electrically conductive bonding structures by metal-to-metal bonding and further embedding a second dummy electrically conductive bonding structure is electrically isolated from the second metal interconnect structures.
12 . The bonded assembly of claim 11 , wherein an entirety of a top surface of the first dummy electrically conductive bonding structure is in contact with a surface of the second bonding-level dielectric layer.
13 . The bonded assembly of claim 11 , wherein the first dummy electrically conductive bonding structure is bonded to the second dummy electrically conductive bonding structure by additional metal-to-metal bonding.
14 . The bonded assembly of claim 11 , wherein the second bonding-level dielectric layer is bonded to the first bonding-level dielectric layer by dielectric-to-dielectric bonding.
15 . A method of forming a semiconductor structure, comprising:
forming first semiconductor devices over a first substrate;
forming first metal interconnect structures embedded in first dielectric material layers over the first semiconductor devices;
forming a first bonding-level dielectric layer over the first dielectric material layers;
forming a first recess cavity and a first dummy recess cavity in the first bonding-level dielectric layer, the first dummy recess cavity having a lesser lateral extent than the first recess cavity;
forming an insulating spacer material layer in the first recess cavity and the first dummy recess cavity and over the first bonding-level dielectric layer;
performing an anisotropic etch process that etches materials of the insulating spacer material layer and the first-bonding-level dielectric layer to form a first-type insulating spacer in a peripheral portion of the first recess cavity and to form a second-type insulating spacer in a peripheral portion of the first dummy recess cavity, such that a first stepped via cavity extends through the first-type insulating spacer and through the first bonding-level dielectric layer to a top surface of one of the first metal interconnect structures, and a second stepped via cavity extends through the second-type insulating spacer and has a bottommost surface that overlies a bottom surface of the first bonding-level dielectric layer; and
forming a first electrically conductive bonding structure in the first stepped via cavity and forming a first dummy electrically conductive bonding structure in the second stepped via cavity to form a first semiconductor die.
16 . The method of claim 15 , wherein the anisotropic etch process comprises a reactive ion etch (RIE) process that generates a polymer material as an etch product which clogs a remaining void in the second stepped via cavity and terminates the RIE process before the bottom surface of the second stepped via cavity reaches the bottom surface of the first bonding-level dielectric layer, while the polymer material does not clog an entire remaining void in the first stepped via cavity, and the RIE process continues until the bottom surface of the first stepped via cavity reaches the bottom surface of the first bonding-level dielectric layer and a top surface of a respective one of the first metal interconnect structures is exposed at the bottom of the respective first stepped via cavity.
17 . The method of claim 15 , wherein the first stepped via cavity has a first vertical cross-sectional profile including a first contoured sidewall comprising a first upper sidewall segment having a first upper taper angle relative to a vertical direction, a first lower sidewall segment having a first lower taper angle relative to the vertical direction, and a first connecting surface segment having a first connecting taper angle relative to the vertical direction, the first connecting taper angle being greater than the first upper taper angle and the first lower taper angle.
18 . The method of claim 17 , wherein:
the first upper sidewall segment comprises a first surface segment of the first-bonding-level dielectric layer; and
a lower portion of the first lower sidewall segment comprises a second surface segment of the first bonding-level dielectric layer.
19 . The method of claim 18 , wherein:
an upper portion of the first lower sidewall segment comprises a lower portion of an inner sidewall of the first-type insulating spacer; and
the first connecting surface segment comprises an upper portion of the inner sidewall of the first-type insulating spacer.
20 . The method of claim 15 , further comprising:
providing a second semiconductor die comprising a second bonding-level dielectric layer embedding a second electrically conductive bonding structure and a second dummy electrically conductive bonding structure; and
bonding the second semiconductor die to the first semiconductor die such that the second electrically conductive bonding structure is bonded to the first electrically conductive bonding structure by metal-to-metal bonding.