Granted Patent B2

US 12,657,123 · App. 18/583,061 · Granted Jun 16, 2026

Inventors: Amit Sharma (Karnataka, IN); Abhinandan Venugopal (Karnataka, IN); Hitesh Golechchha (Karnataka, IN)

Assignee: Sandisk Technologies, Inc.

G06F12/0246

Abstract

Claims (40)

1 . A method, comprising:

determining a communication protocol associated with a host device;

determining performance requirements associated with the communication protocol;

comparing the determined performance requirements to available hardware resources of a memory device;

selecting a memory die programming method and a memory die programming parameter based, at least in part, on the comparison of the determined performance requirements to the available hardware resources, the memory die programming method being selected from a plurality of memory die programming methods arranged in a programming method preference hierarchy; and

configuring the memory device to perform one or more programming operations according to the memory die programming method and the memory die programming parameter.

2 . The method of claim 1 , wherein configuring the memory device comprises configuring firmware of the memory device to perform the one or more programming operations according to the memory die programming method and the memory die programming parameter.

3 . The method of claim 1 , wherein the plurality of memory die programming methods include an on chip copy (OCC) programming method and a copy through controller (CTC) programming method.

4 . The method of claim 1 , wherein the memory die programming parameter is a memory trim parameter.

5 . The method of claim 4 , wherein the memory trim parameter is a programming voltage.

6 . The method of claim 1 , wherein the communication protocol is determined in response to a connection event.

7 . The method of claim 1 , wherein the one or more hardware resources associated with the memory device are selected from a group comprising, a random access memory (RAM) of the memory device, a speed of a controller associated with the memory device, and a direct memory access (DMA) speed associated with the memory device.

8 . The method of claim 1 , further comprising associating configuration information with the host device.

9 . A data storage device, comprising:

a controller; and

a performance determination system associated with the controller and operable to:

determine, in response to a configuration event, performance requirements of a communication protocol utilized by a host device;

compare the determined performance requirements to available hardware resources of the data storage device;

select a memory die programming method from a plurality of memory die programming methods arranged in a programming method preference hierarchy based, at least in part, on the comparison of the determined performance requirements to the available hardware resources; and

configure the data storage device to perform one or more programming operations according to the selected memory die programming method.

10 . The data storage device of claim 9 , wherein the performance determination system is further operable to configure firmware of the data storage device according to the selected memory die programming method.

11 . The data storage device of claim 9 , wherein the plurality of memory die programming methods include an on chip copy (OCC) programming method and a copy through controller (CTC) programming method.

12 . The data storage device of claim 9 , wherein the configuration event is associated with a data storage device connection event.

13 . The data storage device of claim 9 , wherein the data storage device is a removable data storage device.

14 . The data storage device of claim 9 , wherein the performance determination system is further operable to:

associate configuration information of the data storage device with the host device; and

store the configuration information.

15 . The data storage device of claim 14 , wherein the performance determination system is further operable to load the configuration information in response to a determination that the data storage device is reconnected to the host device.

16 . The data storage device of claim 9 , wherein the performance determination system is further operable to:

select a memory die programming parameter based, at least in part, on the determined performance requirements; and

configure the data storage device to perform the one or more programming operations according to the selected memory die programming method and the memory die programming parameter.

17 . The data storage device of claim 16 , wherein the memory die programming parameter is a memory trim parameter.

18 . A data storage device, comprising:

a controller means;

means for determining performance requirements of a communication protocol utilized by a host device;

means for comparing the determined performance requirements to available hardware resources of the data storage device;

means for selecting a memory die programming method and a memory die programming parameter based, at least in part, on the comparison of the determined performance requirements to the available hardware resources, the memory die programming method being selected from a plurality of memory die programming methods arranged in a programming method preference hierarchy; and

means for configuring the data storage device to perform one or more programming operations according to the at least one of the memory die programming method and the memory die programming parameter.

19 . The data storage device of claim 18 , further comprising means for storing configuration information of the data storage device.

20 . The data storage device of claim 18 , wherein the means for determining the performance requirements of the communication protocol associated with host device is operable to determine the performance requirements in response to a configuration event.

Assignments (7)

Continuity (1)

References Cited (10)