IP Library Patent Application 18584729
Patent Application
App. No. 18/584,729

STEP-DOWN PRINTED CIRCUIT BOARD WITH A FLEXIBLE CONNECTOR

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
18/584,729
Abstract

A semiconductor package includes a step-down PCB. The step-down PCB includes a first portion having a first height a second portion having a second height that is less than the first height. The step-down PCB can be a single, unitary structure or have different PCB portions. When the step-down PCB has different PCB portions, a flexible connector mechanically and electrically couples the PCB portions together. Due to the reduced thickness of the second portion, additional semiconductor dies can be added to a stack of semiconductor dies, thereby increasing the capabilities of the semiconductor package. Additionally, the first portion includes contacts for a connector. The connector is used to communicatively couple the semiconductor package to an associated connector slot of a host device.

Claims (33)

1 . A semiconductor package, comprising:

a first printed circuit board (PCB) portion having a first thickness;

a second PCB portion having a second thickness that is less than the first thickness;

a flexible connector provided between the first PCB portion and the second PCB portion, the flexible connector mechanically and electrically connecting the first PCB portion and the second PCB portion;

a plurality of contacts provided on the first PCB portion for electrically coupling the semiconductor package to a connector of a host device; and

a plurality of semiconductor dies provided on the second PCB portion.

2 . The semiconductor package of claim 1 , further comprising one or more passive components mounted on the second PCB portion.

3 . The semiconductor package of claim 1 , wherein at least one of the plurality of semiconductor dies is a NAND memory die.

4 . The semiconductor package of claim 1 , wherein at least one of the plurality of semiconductor dies is an application-specific integrated circuit (ASIC).

5 . The semiconductor package of claim 1 , further comprising a molding compound at least partially covering the second PCB portion.

6 . The semiconductor package of claim 1 , wherein the plurality of contacts are part of an M.2 connector.

7 . The semiconductor package of claim 1 , wherein the plurality of contacts are part of an Enterprise and Datacenter Standard Form Factor (EDSFF) connector.

8 . The semiconductor package of claim 1 , wherein the flexible connector extends from a top portion of the first PCB portion.

9 . The semiconductor package of claim 1 , wherein the flexible connector extends from a middle portion of the first PCB portion.

10 . The semiconductor package of claim 1 , wherein the flexible connector extends from a top portion of the second PCB portion.

11 . The semiconductor package of claim 1 , wherein the flexible connector extends from a middle portion of the second PCB portion.

12 . A semiconductor package, comprising:

a plurality of contacts provided on a first printed circuit board (PCB) portion, the first PCB portion having a first number of layers and a first thickness;

a plurality of semiconductor dies provided on a second PCB portion, the second PCB portion being separate from the first PCB portion and having a second number of layers that is less that the first number of layers and having a second thickness that is less than the first thickness; and

a flexible connector coupling the first PCB portion and the second PCB portion.

13 . The semiconductor package of claim 12 , further comprising a cover at least partially encapsulating the second PCB portion.

14 . The semiconductor package of claim 12 , wherein the plurality of contacts form an M.2 connector.

15 . The semiconductor package of claim 12 , wherein the plurality of contacts form an Enterprise and Datacenter Standard Form Factor (EDSFF) connector.

16 . The semiconductor package of claim 12 , wherein the flexible connector extends from a top portion of the first PCB portion.

17 . The semiconductor package of claim 12 , wherein the flexible connector extends from a middle portion of the second PCB portion.

18 . A semiconductor package, comprising:

a first printed circuit board (PCB) portion having a first thickness;

a second PCB portion having a second thickness that is less than the first thickness;

a flexible connection means provided between the first PCB portion and the second PCB portion, the flexible connection means mechanically and electrically coupling the first PCB portion and the second PCB portion;

a plurality of signal carrying means provided on a surface of the first PCB portion; and

a plurality of semiconductor dies provided on the second PCB portion.

19 . The semiconductor package of claim 18 , further comprising a covering means provided on the second PCB portion.

20 . The semiconductor package of claim 18 , wherein the semiconductor dies are NAND memory dies.

Assignments (7)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT (AR) Recorded May 15, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 067417/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2024
From: KY, JASEN; FONG, LIHWA; YE, NING; MOHANRAJ, NANDHA KUMAR; DHANACHANDRA PRAKASH, JEGATHESE
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 066549/0318 →