PROCESSING CORE INCLUDING INTEGRATED HIGH CAPACITY HIGH BANDWIDTH STORAGE MEMORY

1 . A processing core, comprising:

a signal-carrying medium;

one or more volatile memory tiles electrically coupled to the signal carrying medium;

a processor physically and electrically coupled to an uppermost volatile memory tile of the one or more volatile memory tiles.

2 . The processing core of claim 1 , wherein the one or more volatile memory tiles are one of a DRAM, SRAM, SDRAM and a high bandwidth memory.

3 . The processing core of claim 1 , wherein the one or more volatile memory tiles have a same footprint as the processor.

4 . The processing core of claim 1 , further comprising one or more stacks of high bandwidth memory mounted on the signal-carrying medium around one or more lateral sides of the CBA memory tile.

5 . The processing core of claim 1 , wherein the processor comprises one or more processing cores.

6 . The processing core of claim 1 , wherein the processor is one of a graphics processing unit and an artificial intelligence processor.

7 . The processing core of claim 1 , further comprising a CMOS Bonded Array (CBA) memory tile physically and electrically coupled to the signal carrying medium, the memory tile comprising a first semiconductor tile bonded to a second semiconductor tile, wherein a bottommost volatile memory tile of the one or more memory tiles is physically and electrically coupled to the CBA memory tile.

8 . The processing core of claim 7 , wherein the first semiconductor tile comprises a plurality of memory cells.

9 . The processing core of claim 8 , wherein the second semiconductor tile comprises a CMOS logic circuit for controlling access to the plurality of memory cells.

10 . The processing core of claim 7 , wherein the first semiconductor tile is bonded to the processor and the second semiconductor tile is coupled to the signal-carrying medium.

11 . The processing core of claim 7 , wherein the CBA memory tile is the same footprint as the one or more non-volatile memories and the processor.

12 . A processing core, comprising:

a signal-carrying medium;

one or more volatile memory tiles electrically coupled to the signal-carrying medium, a volatile memory tile of the one or more volatile memory tiles comprising:

a first area comprising integrated memory circuits, and

one or more passthrough zones outside of the first area, the passthrough zones devoid of the integrated memory circuits; and

a processor physically and electrically coupled to an uppermost volatile memory tile of the one or more volatile memory tiles;

wherein the volatile memory tile further comprises:

a first set of electrical connections in the first area electrically coupling the volatile memory tile to the processor, and

a second set of electrical connections in the one or more passthrough zones configured to transfer electrical signals between the processor and signal-carrying medium through the volatile memory tile.

13 . The processing core of claim 12 , wherein the signal-carrying medium is an interposer diced from an interposer wafer.

14 . The processing core of claim 12 , wherein the signal-carrying medium is a wafer comprising a plurality of interposers, the processing core mounted to one of the interposers on the wafer of interposers.

15 . The processing core of claim 12 , further comprising a CMOS bonded to array (CBA) memory tile physically and electrically coupled to the signal carrying medium, the CBA memory tile comprising a memory array tile comprising non-volatile memory arrays, and a CMOS logic circuit tile comprising CMOS logic circuits bonded to the memory array tile.

16 . The processing core of claim 15 , wherein the CBA memory tile comprises a second area comprising the non-volatile memory arrays and the CMOS logic circuits, and a second passthrough zone, aligning with the first passthrough zone of the volatile memory tile, wherein the second passthrough zone is configured to transfer electrical signals between the processor and signal-carrying medium through the CBA memory tile.

17 . The processing core of claim 15 , wherein the CBA memory tile, the one or more volatile memory tiles and the processor have the same footprint.

18 . The processing core of claim 17 , wherein the footprint is a size of a reticle used to define the integrated memory circuits of the volatile memory tile.

19 . A semiconductor wafer processed to include circuitry for a plurality of interposers, comprising:

a plurality of processing cores formed on the plurality of interposers, a processing core of the plurality of processing cores comprising:

a CMOS bonded to array (CBA) memory tile physically and electrically coupled to the interposer, the CBA memory tile comprising a memory array tile comprising non-volatile memory arrays, and a CMOS logic circuit tile comprising CMOS logic circuits bonded to the memory array tile;

one or more volatile memory tiles physically and electrically coupled to the CBA memory tile; and

a processor physically and electrically coupled to an uppermost volatile memory tile of the one or more volatile memory tiles.

20 . The semiconductor wafer of claim 19 , wherein the circuitry includes a first set of electrical connections electrically coupling the plurality of processing cores to each other, and a second set of electrical connections configured to electrically coupling the wafer to system level PCB.