IP Library Assignment 015102/0436
Patent Assignment
Reel/Frame 015102/0436

Assignment of Assignor's Interest

Recorded: 2004-09-09 Pages: 3
Assignors
TAI, HUNG-EN
Executed: 2004-09-02
CHEN, CHIA-YUN
Executed: 2004-09-02
WANG, SHENG-JEN
Executed: 2004-09-02
Assignee
POWERCHIP SEMICONDUCTOR CORP.
NO. 12, LI-HSIN RD. I, SCIENCE-BASED INDUSTRIAL, PARK, HSIN-CHU CITY, TAIWAN
Covered Property (1)
Method of Managing Wafer Defects
Patent: 7,412,090 →
Application: 10/711,310 →
Publication: US 2006/0050950
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of the Address of the Assignee Jun 10, 2008
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 021068/0646 →
Change of Name Jun 28, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049629/0240 →
Assignment of Assignor's Interest Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049746/0981 →