Patent Assignment
Reel/Frame 017649/0016
Release
Recorded: 2006-03-07
Received: 2006-03-09
Pages: 13
Assignor
SILICON VALLEY BANK
Executed: 2006-01-13
Assignee
MATRIX SEMICONDUCTOR, INC.
3230 SCOTT BLVD, SANTA CLARA, CA, 95054, UNITED STATES
Covered Properties
(36)
Tft Mask Rom and Method for Making Same
Application:
09/983,988 →
Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication
Application:
09/939,498 →
Contact and via Structure and Method of Fabrication
Application:
09/939,321 →
Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication
Application:
09/939,431 →
Integrated Circuit Feature Layout for Improved Chemical Mechanical Polishing
Application:
09/935,862 →
Nonvolatile Memory on Soi and Compound Semiconductor Substrates and Method of Fabrication
Application:
09/927,642 →
Low-Cost Three-Dimensional Memory Array
Application:
09/928,969 →
Vertically-Stacked, Field-Programmable, Nonvolatile Memory and Method of Fabrication
Application:
09/928,536 →
Monolithic Three Dimensional Array of Charge Storage Devices Containing a Planarized Surface
Application:
09/927,648 →
Anti-fuse memory cell with asymmetric breakdown voltage
Application:
09/918,307 →
Process for Fabricating a Dielectric Film Using Plasma Oxidation
Application:
09/918,853 →
Current Sensing Method and Apparatus Particularly Useful for a Memory Array of Cells Having Diode-Like Characteristics
Application:
09/896,468 →
Method and Apparatus for Writing Memory Arrays Using External Source of High Programming Voltage
Application:
09/897,785 →
Memory Device and Method for Sensing While Programming a Non-Volatile Memory Cell
Application:
09/896,815 →
Memory Array Incorporating Noise Detection Line
Application:
09/897,704 →
Method and Apparatus for Biasing Selected and Unselected Array Lines When Writing a Memory Array
Application:
09/897,771 →
Golf Ball with Sulfur Cured Inner Core Component
Application:
09/894,960 →
Method and Apparatus for Discharging Memory Array Lines
Application:
09/897,784 →
Three-Dimensional Memory Array Incorporating Serial Chain Diode Stack
Application:
09/897,705 →
Memory Device with Row and Column Decoder Circuits Arranged in a Checkerboard Pattern Under a Plurality of Memory Arrays
Application:
09/896,814 →
Method for Reading Data in a Write-Once Memory Device Using a Write-Many File System
Application:
09/878,138 →
Memory Device and Method for Storing and Reading a File System Structure in a Write-Once Memory Array
Application:
09/877,719 →
Memory Device and Method for Storing and Reading Data in a Write-Once Memory Array
Application:
09/877,720 →
Method of Preventing Autodoping
Application:
09/859,282 →
High-Voltage Transistor and Fabrication Process
Application:
09/823,503 →
Method for Field-Programming a Solid-State Memory Device with a Digital Media File
Application:
09/823,489 →
Three-Dimensional Memory Array and Method of Fabrication
Application:
09/814,727 →
Integrated Circuit Current Source with Switched Capacitor Feedback
Application:
09/809,884 →
Multi-Stage Charge Pump
Application:
09/809,878 →
Memory Card with Enhanced Testability and Methods of Making and Using the Same
Application:
09/788,864 →
Method of Generating Integrated Circuit Feature Layout for Improved Chemical Mechanical Polishing
Application:
09/775,761 →
Memory Device and Method for Reading Data Stored in a Portion of a Memory Device Unreadable by a File System of a Host Device
Application:
09/775,939 →
Wafer surface that facilitates particle removal
Application:
09/776,009 →
Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays
Application:
09/775,956 →
Structure and Method for Wafer Comprising Dielectric and Semiconductor
Application:
09/776,000 →
Solid-state memory device storing program code and methods for use therewith
Application:
09/775,745 →