TFT mask ROM and method for making same
View Patent ↗There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
1. A monolithic three dimensional TFT mask ROM array, comprising a plurality of device levels, wherein each device level of the plurality of device levels comprises a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
2. The array of claim 1 , further comprising at least one interlevel insulating layer located between adjacent device levels.
3. The array of claim 1 , wherein adjacent device levels contact each other.
4. The array of claim 1 , wherein the second set of TFTs comprises a set of totally disabled TFTs.
5. The array of claim 1 , wherein the second set of TFTs comprises a plurality of totally disabled TFTs and a plurality of partially disabled TFTs.
6. The array of claim 1 , wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively removed or selectively doped to increase a threshold voltage of said TFTs to render said TFTs partially or totally inoperative.
7. The array of claim 1 , wherein:
at least a portion of channel regions of a first subset of the TFTs of the second set have been selectively removed to render the first subset of the TFTs totally inoperative; and
at least a portion of channel regions of a second subset of the TFTs of the second set have been selectively doped to increase a threshold voltage of said TFTs to render said TFTs partially inoperative.
8. The array of claim 1 , wherein:
at least a portion of channel regions of a first subset of the TFTs of the second set have been selectively doped to increase a threshold voltage of said TFTs to render said TFTs totally inoperative; and
at least a portion of channel regions of a second subset of the TFTs of the second set have been selectively doped to increase a threshold voltage of said TFTs to render said TFTs partially inoperative.
9. The array of claim 1 , wherein the array comprises:
a substrate;
a first device level over the substrate;
a first interlevel insulating layer over the first device level; and
a second device level over the first interlevel insulating layer.
10. The array of claim 9 , further comprising:
a second interlevel insulating layer over the second device level;
a third device level over the second interlevel insulating layer;
a third interlevel insulating layer over the third device level; and
a fourth device level over the third interlevel insulating layer.
11. The array of claim 9 , wherein:
the TFTs are selected from one or more of top gate co-planar TFTs, top gate staggered TFTs, bottom gate co-planar TFTs and bottom gate staggered TFTs; and
an effective cell area of the array is 4F 2 /N, where F is a minimum feature size and N is a number of device levels.
12. The array of claim 9 , further comprising:
a first plurality of spaced apart conductors disposed at a first height above the substrate in a first direction;
a second plurality of spaced apart rail stacks disposed at a second height in a second direction different from the first direction, each rail stack including:
a first semiconductor layer whose first surface is in contact with said first plurality of spaced apart conductors;
a conductive film; and
a gate insulating film disposed between a second surface of the first semiconductor layer and the conductive film; and
wherein the TFTs are formed at intersections of two adjacent first rails and the second rail stack, such that the conductive film comprises a gate of the TFTs, portions of the first semiconductor layer comprise TFT channel regions and the first rails comprise at least a portion of the TFT source and drain regions.
13. A method of making a monolithic three dimensional TFT mask ROM array, comprising:
forming a first device level comprising a plurality of TFTs over a substrate;
forming a first mask over the first device level;
partially or totally disabling a first set of TFTs in the first device level;
forming a second device level comprising a plurality of TFTs over the first device level;
forming a second mask over the second device level; and
partially or totally disabling a second set of TFTs in the second device level;
wherein:
the array comprises a plurality of device levels; and
each device level of the plurality of device levels comprises a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
14. The array of claim 13 , further comprising forming a first interlevel insulating layer between the first device level and the second device level.
15. The array of claim 13 , wherein the second device level is formed directly on the first device level.
16. The method of claim 13 , wherein the first and the second sets of TFTs are totally disabled.
17. The method of claim 13 , wherein some TFTs are partially disabled and other TFTs are totally disabled.
18. The method of claim 13 , wherein:
the step of forming the first mask over the first device level comprises forming a photoresist layer over a semiconductor channel layer in the first device level;
the step of forming the second mask over the second device level comprises forming a photoresist layer over a semiconductor channel layer in the second device level; and
the steps of disabling comprise selectively etching at least a portion of the semiconductor channel layer exposed through the first or the second mask or selectively doping at least a portion of the semiconductor channel layer exposed through the first or the second mask.
19. The method of claim 13 , further comprising:
selectively etching at least a portion of channel regions of a first plurality of TFTs exposed through the first or the second mask to totally disable the first plurality of TFTs; and
selectively doping at least a portion of channel regions of a second plurality of TFTs exposed through the other of the first or the second mask to partially disable the second plurality of TFTs.
20. The method of claim 13 , further comprising:
selectively doping at least a portion of channel regions of a first plurality of TFTs exposed through the first or the second mask to totally disable the first plurality of TFTs; and
selectively doping at least a portion of channel regions of a second plurality of TFTs exposed through the first or the second mask to partially disable the second plurality of TFTs.
21. The method of claim 13 , wherein the TFTs are selected from one or more of top gate co-planar TFTs, top gate staggered TFTs, bottom gate co-planar TFTs and bottom gate staggered TFTs.
22. The method of claim 13 , wherein the step of forming the first device level comprises:
forming a first plurality of spaced apart conductors disposed at a first height above the substrate in a first direction;
forming a first insulating layer over the first conductors;
planarizing the first insulating layer, such that the first insulating layer is located between the first conductors;
forming a first semiconductor layer whose first surface is in contact with said first plurality of spaced apart conductors;
forming a conductive film;
forming a gate insulating film disposed between a second surface of the first semiconductor layer and the conductive film; and
patterning the first semiconductor layer, the gate insulating film and the conductive film to form a second plurality of spaced apart rail stacks disposed at a second height in a second direction different from the first direction.
23. The method of claim 22 , wherein:
the first plurality of conductors comprise first rails comprising polysilicon layers in contact with metal or a metal silicide layers;
the first semiconductor layer comprises a polysilicon layer;
the gate insulating layer comprises a portion of a charge storage region;
the conductive film comprises a polysilicon layer and a metal silicide layer; and
the TFTs are formed at intersections of two adjacent first rails and the second rail stack, such that the conductive film comprises a gate of the TFTs, portions of the first semiconductor layer comprise TFT channel regions and the polysilicon layers of the first rails comprise at least a portion of the TFT source and drain regions.
24. The method of 23 , claim wherein the step of disabling a first set of TFTs in the first device level comprises forming a mask over the first semiconductor layer and selectively etching unmasked portions of the first semiconductor layer or selectively implanting ions into unmasked portions of the first semiconductor layer.