Patent Assignment
Reel/Frame 017718/0550
Release of Security Interest
Recorded: 2006-06-05
Received: 2006-06-05
Pages: 4
Assignor
SILICON VALLEY BANK
Executed: 2006-01-13
Assignee
SANDISK 3D LLC
601 MCCARTHY BOULEVARD, MILPITAS, CA, 95035, UNITED STATES
Covered Properties
(55)
Gate dielectric structures for integrated circuits and methods for making and using such gate dielectric structures
Application:
10/079,472 →
Anti-Fuse Memory Cell with Asymmetric Breakdown Voltage
Application:
10/027,466 →
Method for Making a Write-Once Memory Device Read Compatible with a Write-Many File System
Application:
10/023,468 →
Memory Device and Method for Redundancy/Self-Repair
Application:
10/024,646 →
Memory Device and Method for Storing Bits in Non-Adjacent Storage Locations in a Memory Array
Application:
10/024,647 →
Memory Device and Method for Dynamic Bit Inversion
Application:
10/023,466 →
Method for Altering a Word Stored in a Write-Once Memory Device
Application:
10/023,200 →
Integrated Circuit Memory Array with Fast Test Mode Utilizing Multiple Word Line Selection and Method Therefor
Application:
09/990,894 →
Integrated Circuit Incorporating Dual Organization Memory Array
Application:
09/990,901 →
Memory Array Organization and Related Test Method Particularly Well Suited for Integrated Circuits Having Write-Once Memory Arrays
Application:
10/002,268 →
Charge Pump Circuit
Application:
10/002,856 →
Dummy Wafers and Methods for Making the Same
Application:
10/036,291 →
Metal Structures for Integrated Circuits and Methods for Making the Same
Application:
10/045,653 →
Three-Dimensional, Mask-Programmed Read Only Memory
Application:
10/010,643 →
Tft Mask Rom and Method for Making Same
Application:
09/983,988 →
Write-Many Memory Device and Method for Limiting a Number of Writes to the Write-Many Memory Device
Application:
09/972,787 →
Thin Film Transistors with Vertically Offset Drain Regions
Application:
09/961,278 →
Memory Device and Method for Selectable Sub-Array Activation
Application:
09/943,655 →
Memory Device and Method for Temperature-Based Control Over Write and/or Read Operations
Application:
09/944,613 →
Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication
Application:
09/939,498 →
Contact and via Structure and Method of Fabrication
Application:
09/939,321 →
Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication
Application:
09/939,431 →
Integrated Circuit Feature Layout for Improved Chemical Mechanical Polishing
Application:
09/935,862 →
Digital Memory Method and System for Storing Multiple Bit Digital Data
Application:
09/932,701 →
Low Resistivity Titanium Silicide on Heavily Doped Semiconductor
Application:
09/928,975 →
Nonvolatile Memory on Soi and Compound Semiconductor Substrates and Method of Fabrication
Application:
09/927,642 →
Molded Memory Module and Method of Making the Module Absent a Substrate Support
Application:
09/928,767 →
Low-Cost Three-Dimensional Memory Array
Application:
09/928,969 →
Vertically-Stacked, Field-Programmable, Nonvolatile Memory and Method of Fabrication
Application:
09/928,536 →
Monolithic Three Dimensional Array of Charge Storage Devices Containing a Planarized Surface
Application:
09/927,648 →
Anti-fuse memory cell with asymmetric breakdown voltage
Application:
09/918,307 →
Process for Fabricating a Dielectric Film Using Plasma Oxidation
Application:
09/918,853 →
Method and Apparatus for Writing Memory Arrays Using External Source of High Programming Voltage
Application:
09/897,785 →
Memory Device and Method for Sensing While Programming a Non-Volatile Memory Cell
Application:
09/896,815 →
Memory Array Incorporating Noise Detection Line
Application:
09/897,704 →
Method and Apparatus for Biasing Selected and Unselected Array Lines When Writing a Memory Array
Application:
09/897,771 →
Method and System for Increasing Programming Bandwidth in a Non-Volatile Memory Device
Application:
09/895,960 →
Method and Apparatus for Discharging Memory Array Lines
Application:
09/897,784 →
Three-Dimensional Memory Array Incorporating Serial Chain Diode Stack
Application:
09/897,705 →
Memory Device with Row and Column Decoder Circuits Arranged in a Checkerboard Pattern Under a Plurality of Memory Arrays
Application:
09/896,814 →
Memory Device and Method for Storing and Reading a File System Structure in a Write-Once Memory Array
Application:
09/877,719 →
Memory Device and Method for Storing and Reading Data in a Write-Once Memory Array
Application:
09/877,720 →
Method of Preventing Autodoping
Application:
09/859,282 →
High-Voltage Transistor and Fabrication Process
Application:
09/823,503 →
Method for Field-Programming a Solid-State Memory Device with a Digital Media File
Application:
09/823,489 →
Three-Dimensional Memory Array and Method of Fabrication
Application:
09/814,727 →
Integrated Circuit Current Source with Switched Capacitor Feedback
Application:
09/809,884 →
Multi-Stage Charge Pump
Application:
09/809,878 →
Memory Card with Enhanced Testability and Methods of Making and Using the Same
Application:
09/788,864 →
Method of Generating Integrated Circuit Feature Layout for Improved Chemical Mechanical Polishing
Application:
09/775,761 →
Memory Device and Method for Reading Data Stored in a Portion of a Memory Device Unreadable by a File System of a Host Device
Application:
09/775,939 →
Wafer surface that facilitates particle removal
Application:
09/776,009 →
Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays
Application:
09/775,956 →
Structure and Method for Wafer Comprising Dielectric and Semiconductor
Application:
09/776,000 →
Solid-state memory device storing program code and methods for use therewith
Application:
09/775,745 →