Low resistivity titanium silicide on heavily doped semiconductor
View Patent ↗Low resistivity, C54-phase TiSi 2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about 2.4 times the thickness of the subsequently deposited Ti film. Upon thermal annealing above 750° C., the undoped amorphous Si is consumed by the reaction of Ti+Si to form TiSi 2 , forming a low-resistivity, C54-phase TiSi 2 film on top of heavily doped polysilicon. The annealing temperature required to form C54 phase TiSi 2 is reduced by consuming undoped amorphous Si in the reaction of Ti and Si, as compared with heavily doped polysilicon. Narrow lines (<0.3 μm) of low-resistivity, C54-phase TiSi 2 films on heavily doped polysilicon are thus achieved.
1. A semiconductor structure comprising:
a first semiconductor region characterized by a dopant concentration greater than 1×10 19 /cm 3 ;
a second semiconductor region overlying the first semiconductor region, said second semiconductor region comprising silicon and characterized by a dopant concentration less than 1×10 18 /cm 3 and a thickness t1; and
a layer comprising titanium directly overlying the second semiconductor region, said layer characterized by a line width no greater than 0.3 μm and a thickness t2, wherein t1>1.2t2;
t1/t2 being sufficiently small that, when the layer is reacted with the second semiconductor region to form titanium disilicide, the titanium disilicide is in ohmic contact with the first semiconductor region;
t1/t2 being sufficiently large that, when the layer is reacted with the second semiconductor region to form titanium disilicide, the titanium disilicide anneals to a phase with a sheet resistance less than 3 ohms/square.
2. The invention of claim 1 wherein t1≧2.2t2.
3. The invention of claim 1 wherein t1=2.3t2, ±0.1t2.
4. The invention of claim 1 wherein t1 is about 600 Å and t2 is about 250 Å.
5. The invention of claim 1 wherein the dopant concentration of the first semiconductor region is greater than 1×10 20 /cm 3 .
6. The invention of claim 1 or 5 wherein the first semiconductor region is doped primarily with boron.
7. A semiconductor structure comprising:
a first semiconductor region characterized by a boron dopant concentration greater than 1×10 20 /cm 3 ; and
a set of titanium suicide conductors directly overlying the first semiconductor region and in ohmic contact therewith, each said conductor characterized by a width no greater than 0.3 μm, and at least 90% of said conductors characterized by a sheet resistance less than 3 ohms/squarel;
wherein the set of titanium silicide conductors is formed, in part, by a second semiconductor region overlying the first semiconductor region, said second semiconductor region comprising silicon and characterized by a dopant concentration less than 1×10 18 /cm 3 .
8. The semiconductor structure of claim 1 or 7 wherein the semiconductor structure comprises a 3-D memory array, wherein the 3-D memory array comprises a plurality of memory cells arranged in a plurality of layers stacked vertically above one another in a single chip.