Patent Assignment
Reel/Frame 019063/0771
Assignment of Assignor's Interest
Recorded: 2007-03-26
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CALIFORNIA, 94088-3453
Covered Properties
(35)
Flash Eeprom Array with High Endurance
Patent:
5,335,198 →
Application:
08/057,583 →
Output Buffer Circuit for a Low Voltage Eprom Q
Patent:
5,367,206 →
Application:
08/078,711 →
System for Allowing a Content Addressable Memory to Operate with Multiple Power Voltage Levels
Patent:
5,357,458 →
Application:
08/083,736 →
Distributed Negative Gate Power Supply
Patent:
5,406,517 →
Application:
08/109,881 →
Independent Array Grounds for Flash Eeprom Array with Paged Erase Architecture
Patent:
5,365,484 →
Application:
08/109,887 →
Sector-Based Redundancy Architecture
Patent:
5,349,558 →
Application:
08/112,033 →
Boosted and Regulated Gate Power Supply with Reference Tracking for Multi-Density and Low Voltage Supply Memories
Patent:
5,511,026 →
Application:
08/160,578 →
Programmed Reference
Patent:
5,828,601 →
Application:
08/160,582 →
Method and Apparatus for Programming Memory Devices
Patent:
5,530,803 →
Application:
08/227,755 →
Method Protecting a Stacked Gate Edge in a Semiconductor Device from Self Aligned Source (Sas) Etch
Patent:
5,470,773 →
Application:
08/233,174 →
Supply Voltage-Independent Reference Voltage Circuit
Patent:
5,955,874 →
Application:
08/265,583 →
High Energy Buried Layer Implant to Provide a Low Resistance P-Well in a Flash Eprom Array
Patent:
5,541,875 →
Application:
08/269,478 →
Multistepped Threshold Convergence for a Flash Memory Array
Patent:
5,576,991 →
Application:
08/269,540 →
Self-Aligned Buried Channel/Junction Stacked Gate Flash Memory Cell
Patent:
5,468,981 →
Application:
08/299,868 →
Self-Aligned Buried Channel/Junction Stacked Gate Flash Memory Cell
Patent:
5,574,685 →
Application:
08/299,876 →
Method for Eliminating of Cycling-Induced Electron Trapping in the Tunneling Oxide of 5 Volt Only Flash Eeproms
Patent:
5,485,423 →
Application:
08/320,368 →
Non-Volatile Memory Structure Including Protection and Structure for Maintaining Threshold Stability
Patent:
5,457,336 →
Application:
08/322,811 →
Layered Low Dielectric Constant Technology
Patent:
5,534,731 →
Application:
08/330,871 →
Novel Processing Techniques for Achieving Production-Worthy, Low Dielectric, Low Interconnect Resistance and High Performance Ics
Patent:
5,550,405 →
Application:
08/360,856 →
Method for Tightening Vt Distribution of 5 Volt-Only Flash Eeproms
Patent:
5,481,494 →
Application:
08/362,346 →
Method of Erasing Uprom Transistors
Patent:
5,656,521 →
Application:
08/371,704 →
Methods for Bulk (or Byte) Charging and Discharging an Array of Flash Eeprom Memory Cells
Patent:
5,491,657 →
Application:
08/393,636 →
Method of Making Flash Eeprom Memory with Reduced Column Leakage Current
Patent:
5,482,881 →
Application:
08/403,460 →
Flash Eeprom Memory with Improved Discharge Speed Using Substrate Bias and Method Therefor
Patent:
5,617,357 →
Application:
08/420,989 →
Method for Protecting a Stacked Gate Edge in a Semiconductor Device from Self Aligned Source (Sas) Etch
Patent:
5,534,455 →
Application:
08/433,267 →
Layered Low Dielectric Constant Technology
Patent:
5,693,566 →
Application:
08/459,957 →
Method and System for Protecting a Stacked Gate Edge in a Semi- Conductor Device from Self Aligned Source (Sas) Etch in a Semi- Conductor Device
Patent:
5,517,443 →
Application:
08/460,603 →
Novel Processing Techniques for Achieving Production-Worthy, Low Dielectric, Low Interconnect Resistance and High Performance Ic
Patent:
5,679,608 →
Application:
08/463,448 →
Flash Eeprom Array with Floating Substrate Erase Operation
Patent:
5,598,369 →
Application:
08/484,252 →
Flash Eeprom Array with Floating Substrate Erase Operation
Patent:
5,561,620 →
Application:
08/508,425 →
Watchdog System Having Data Differentiating Means for Use in Monitoring of Semiconductor Wafer Testing Line
Patent:
5,726,920 →
Application:
08/537,116 →
Novel Processing Techniques for Achieving Production-Worthy, Low Dielectric, Low Interconnect Resistance and High Performance Ics
Patent:
5,965,934 →
Application:
08/681,141 →
A Flash Eeprom Memory with Reduced Column Leakage Current and Method Therefor
Patent:
5,652,447 →
Application:
08/684,920 →
Silicon Nitride Etch Process with Critical Gain
Patent:
6,593,245 →
Application:
08/690,848 →
Semiconductor Device from Self-Aligned Source (Sas) Etch in a Semiconductor Device
Patent:
5,693,972 →
Application:
08/769,178 →
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 19, 2007
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION INC.
Reel/Frame 019028/0599 →
Security Agreement
Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
Release of Security Interest
Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036019/0156 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036021/0118 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036019/0326 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036018/0546 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036018/0728 →
Partial Release of Security Interest in Patents
Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
Assignment of Assignor's Interest
Sep 28, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 044051/0244 →
Release of Security Interest
Sep 28, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 044052/0280 →
Assignment of Assignor's Interest
Oct 2, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 044094/0669 →