IP Library › Assignment 030020/0494
Patent Assignment
Reel/Frame 030020/0494

Assignment of Assignor's Interest

Recorded: 2013-03-15 Pages: 3
Assignors
NEMAZIE, SIAMACK
Executed: 2013-03-14
MANDAPURAM, ANILKUMAR
Executed: 2013-03-14
Assignee
AVALANCHE TECHNOLOGY, INC.
48371 FREMONT BLVD., SUITE 101, FREMONT, CALIFORNIA, 94538
Covered Property (1)
Method for Reducing Effective Raw Bit Error Rate in Multi-Level Cell Nand Flash Memor
Patent: 8,656,255 →
Application: 13/840,327 →
Related Assignments (6)
Other recorded transfers of the patent in this record — the chain of ownership.
Security Interest Apr 18, 2017
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 042273/0813 →
Security Interest Feb 13, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 051930/0396 →
Security Interest Jul 8, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: SILICON VALLEY BANK
Reel/Frame 053156/0223 →
Security Interest Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057213/0050 →
Security Interest Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057217/0674 →
Security Interest Mar 18, 2022
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 059436/0203 →