Patent Assignment
Reel/Frame 035257/0406
Release
Recorded: 2015-03-09
Pages: 11
Assignor
SILICON VALLEY BANK
Executed: 2005-09-15
Assignee
RAMTRON INTERNATIONAL CORPORATION
1850 RAMTRON DRIVE, COLORADO SPRINGS, COLORADO, 80921
Covered Properties
(94)
Method of Making Ferroelectric Memory Devices
Patent:
5,024,964 →
Application:
06/793,186 →
Self Restoring Ferroelectric Memory
Patent:
4,873,664 →
Application:
07/013,746 →
Data Storage Device and Method of Using a Ferroeloctric Capacitance Divider
Patent:
4,853,893 →
Application:
07/069,389 →
Method of Operating a Memory Cell with Volatile and Non-Volatile Portions Having Ferroelectric Capacitors
Patent:
4,809,225 →
Application:
07/069,390 →
Ferroelectric Retention Method
Patent:
4,893,272 →
Application:
07/184,996 →
Non-Volatile Memory Cell and Sensing Method
Patent:
4,888,733 →
Application:
07/243,414 →
One Transistor Memory Cell with Programmable Capacitance Divider
Patent:
4,914,627 →
Application:
07/292,776 →
Sram with Programmable Capacitance Divider
Patent:
4,918,654 →
Application:
07/292,818 →
Dram with Programmable Capacitance Divider
Patent:
4,910,708 →
Application:
07/292,891 →
Multilayer Electrodes for Integrated Circuit Capacitors
Patent:
5,005,102 →
Application:
07/368,668 →
Monolithic Semiconductor Integrated Circuit Ferroelectric Memory Device
Patent:
5,214,300 →
Application:
07/763,371 →
Structure of High Dielectric Constant Metal/ Dielectric/Semiconductor Capacitor for Use as the Storage Capacitor in Memory Devices
Patent:
5,338,951 →
Application:
07/788,547 →
Non-Volatile Ferroelectric Memory with Folded Bit Lines and Method of Making the Same
Patent:
5,371,699 →
Application:
07/977,825 →
Ozone Gas Processing for Ferroelectric Memory Circuits
Patent:
5,374,578 →
Application:
08/064,746 →
Ferroelectric-Based Ram Sensing Scheme Including Bit-Line Capacitance Isolation
Patent:
5,381,364 →
Application:
08/083,883 →
Ferroelectrid Memory Device with Capacitor Electrode in Direct Contact with Source Region
Patent:
5,866,926 →
Application:
08/093,790 →
Semiconductor Device Having a Ferroelectric Film in a Through-Hole
Patent:
5,369,296 →
Application:
08/139,340 →
Ferroelectric Capacitor Renewal Method
Patent:
5,525,528 →
Application:
08/200,216 →
Passivation Method and Structure for a Ferroelectric Integrated Circuit Using Hard Ceramic Materials or the Like
Patent:
5,438,023 →
Application:
08/212,495 →
Semiconductor Device Having a Transistor, a Ferroelectric Capacitor and a Hydrogen Barrier Film
Patent:
5,523,595 →
Application:
08/238,802 →
Stacked Ferroelectric Memory Cell and Method
Patent:
5,495,117 →
Application:
08/257,954 →
Semiconductor Device with a Conductive Reaction-Preventing Film
Patent:
5,475,248 →
Application:
08/303,134 →
Voltage Reference for a Ferroelectric 1T/1C Based Memory
Patent:
5,572,459 →
Application:
08/306,686 →
Passivation Method and Structure Using Hard Ceramic Materials or the Like
Patent:
5,578,867 →
Application:
08/394,467 →
Circuit and Method for Reducing a Compensation of a Ferroelectric Capacitor by Multiple Pulsing of the Plate Line Following a Write Operation
Patent:
5,592,410 →
Application:
08/420,293 →
Ferroelectric Memory Sensing Scheme Using Bit Lines Precharged to a Logic One Voltage
Patent:
5,530,668 →
Application:
08/420,752 →
Low Loss, Regulated Charge Pump with Integrated Ferroelectric Capacitors
Patent:
5,889,428 →
Application:
08/468,861 →
Ferroelectric Nonvolatile Random Access Memory Utilizing Self-Bootstrapping Plate Line Segment Drivers
Patent:
5,598,366 →
Application:
08/515,558 →
Method for Making a Ferroelectrric Memory Cell with a Ferroelectric Capacitor Overlying a Memory Transistor
Patent:
5,580,814 →
Application:
08/527,175 →
Use of Calcium and Strontium Dopants to Improve Retention Performance in a Pzt Ferroelectric Film
Patent:
5,969,935 →
Application:
08/616,856 →
Method of Measuring Retention Performance and Imprint Degradation of Ferroelectric Films
Patent:
6,008,659 →
Application:
08/616,913 →
Iridium Oxide Local Interconnect
Patent:
5,838,605 →
Application:
08/618,884 →
Bootstrapping Circuit Utilizing a Ferroelectric Capacitor
Patent:
5,774,392 →
Application:
08/620,799 →
Voltage Reference for a Ferroelectric 1T/Ic Based Memory
Patent:
5,822,237 →
Application:
08/634,445 →
Low Voltage Bootstrapping Circuit
Patent:
5,999,461 →
Application:
08/663,032 →
Circuit and Method for Reducing Compensation of a Ferroelectric Capacitor by Multiple Pulsing of the Plate Line Following a Write Operation
Patent:
5,815,430 →
Application:
08/691,132 →
Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent:
5,920,453 →
Application:
08/700,076 →
Bandgap Reference Based Power-on Detect Circuit Including a Supression Circuit
Patent:
5,852,376 →
Application:
08/702,363 →
Semiconductor Memory Device
Patent:
5,818,771 →
Application:
08/723,367 →
Partially or Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent:
5,864,932 →
Application:
08/728,740 →
Data Processor Incorporating a Ferroelectric Memory Array Selectably Configurable as Read/Write and Read Only Memory
Patent:
5,890,199 →
Application:
08/734,802 →
Partially or Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent:
6,027,947 →
Application:
08/828,157 →
Dual-Level Metalization Method for Integrated Circuit Ferroelectric Devices
Patent:
5,902,131 →
Application:
08/853,527 →
Use of Calcium and Strontium Dopants to Improve Retention Performance in a Pzt Ferroelectric Film
Patent:
5,800,683 →
Application:
08/861,674 →
Multi-Layer Approach for Optimizing Ferroelectric Film Performance
Patent:
6,080,499 →
Application:
08/896,684 →
Voltage Boost Circuit and Operation Thereof at Low Power Supply Voltages
Patent:
5,854,568 →
Application:
08/915,054 →
Plate Line Segmentation in a 1T/1C Ferroelectric Memory
Patent:
5,995,406 →
Application:
08/970,448 →
Reference Cell for a 1T/1C Ferroelectric Memory
Patent:
5,956,266 →
Application:
08/970,452 →
Sensing Methodology for a 1T/1C Ferroelectric Memory
Patent:
5,880,989 →
Application:
08/970,453 →
Column Decoder Configuration for a 1T/1C Ferroelectric Memory
Patent:
5,892,728 →
Application:
08/970,454 →
Reference Cell Configuration for a 1T/1C Ferroelectric Memory
Patent:
5,986,919 →
Application:
08/970,518 →
Sense Amplifier Configuration for a 1T/1C Ferroelectric Memory
Patent:
5,969,980 →
Application:
08/970,519 →
Memory Cell Configuration for a 1T/1C Ferroelectric Memory
Patent:
6,028,783 →
Application:
08/970,520 →
Plate Line Driver Circuit for a 1T/1C Ferroelectric Memory
Patent:
5,978,251 →
Application:
08/970,522 →
Integrated Circuit Memory Device Incorporating a Non-Volatile Memory Array and a Relatively Faster Access Time Memory Cache
Patent:
6,263,398 →
Application:
09/021,132 →
Ferroelectric Thin Films and Solutions: Compositions
Patent:
6,203,608 →
Application:
09/061,362 →
Multi-Layer Approach for Optimizing Ferroelectric Film Performance
Patent:
6,090,443 →
Application:
09/064,465 →
Completely Encapsulated Top Electrode of a Ferroelectric Capacitor Using a Lead-Enhanced Escapsulation Layer
Patent:
6,211,542 →
Application:
09/085,280 →
Hydrogen Barrier Encapsulation Techniques for the Control of Hydrogen Induced Degradation of Ferroelectric Capacitors in Conjunction with Multilevel Metal Processing for Non-Volatile Integrated Circuit Memory Devices
Patent:
6,249,014 →
Application:
09/164,952 →
Method of Manufacturing Ferroelectric Memory Device Useful for Preventing Hydrogen Line Degradation
Patent:
6,174,735 →
Application:
09/177,392 →
Method of Forming Oxide Local Interconnect
Patent:
5,985,713 →
Application:
09/183,545 →
Barrier Layer to Protect a Ferroelectric Capacitor After Contact Has Been Made to the Capacitor Electrode
Patent:
6,242,299 →
Application:
09/283,166 →
Ferroelectric Non-Volatile Latch Circuits
Patent:
6,141,237 →
Application:
09/351,563 →
Yield Enhancement Technique for Integrated Circuit Processing to Reduce Effects of Undesired Dielectric Moisture Retention and Subsequent Hydrogen Out-Diffusion
Patent:
6,190,926 →
Application:
09/356,534 →
Multi-Layer Approach for Optimizing Ferroelectric Film Performance
Patent:
6,287,637 →
Application:
09/427,644 →
Plate Line Driver Circuit for a 1T/1C Ferroelectric Memory
Patent:
6,185,123 →
Application:
09/465,724 →
Method of Fabricating Partially or Completely Encapsulated Top Electrode of a Ferroelectric Capacitor
Patent:
6,150,184 →
Application:
09/505,106 →
High Temperature Deposition of Pt/Tiox for Bottom Electrodes
Patent:
6,682,772 →
Application:
09/556,255 →
Enhanced Process Capability for Sputtered Ferroelectric Films Using Low Frequency Pulsed Dc and Rf Power Supplies
Patent:
6,455,326 →
Application:
09/570,680 →
Ferroelectric memory device structure useful for preventing hydrogen line degradation
Patent:
6,201,726 →
Application:
09/588,153 →
Nonvolatile Octal Latch and D-Type Register
Patent:
6,362,675 →
Application:
09/614,157 →
Method of Manufacturing Ferroelectric Memory Device Structure Useful for Preventing Hydrogen Line Degradation
Patent:
6,358,755 →
Application:
09/641,091 →
Reference cell configuration for a 1T/1C ferroelectric memory
Patent:
6,252,793 →
Application:
09/663,121 →
Ferroelectric voltage boost circuits
Patent:
6,275,425 →
Application:
09/714,879 →
Sense Amplifier Configuration for a 1T/1C Ferroelectric Memory
Hydrogen Barrier Encapsulation Techniques for the Control of Hydrogen Induced Degradation of Ferroelectric Capacitors in Conjunction with Multilevel Metal Processing for Non-Volatile Integrated Circuit Memory Devices
Structure for Masking Integrated Capacitors of Particular Utility for Ferroelectric Memory Integrated Circuits
Method for Manufacturing a Ferroelectric Memory Cell Including Co-Annealing
Patent:
6,376,259 →
Application:
09/816,425 →
Charge Pump or Other Charge Storage Capacitor Including Pzt Layer for Combined Use as Encapsulation Layer and Dielectric Layer of Ferroelectric Capacitor and a Method for Manufacturing the Same
Two Stage Low Voltage Ferroelectric Boost Circuit
Cmos Boosting Circuit Utilizing Ferroelectric Capacitors
Patent:
6,430,093 →
Application:
09/864,858 →
Capacitively Coupled Ferroelectric Random Access Memory Cell and a Method for Manufacturing the Same
Pzt Layer as a Temporary Encapsulation and Hard Mask for a Ferroelectric Capacitor
Patent:
6,423,592 →
Application:
09/893,218 →
Ferroelectric Random Access Memory Configurable Output Driver Circuit
Patent:
6,445,608 →
Application:
09/950,560 →
Self Referencing 1T/1C Ferroelectric Random Access Memory
Patent:
6,459,609 →
Application:
10/022,119 →
Ferroelectric Non-Volatile Logic Elements
Ferroelectric Memory with Bit-Plate Parallel Architecture and Operating Method Thereof
Patent:
6,538,914 →
Application:
10/114,535 →
Capacitance Sensing Technique for Ferroelectric Random Access Memory Arrays
Method for Producing Crystallographically Textured Electrodes for Textured Pzt Capacitors
Method for Producing Crystallographically Textured Electrodes for Textured Pzt Capacitors
Ferroelectric Random Access Memory Configurable Output Driver Circuit
Column Decoder Configuration for a 1T/1C Memory
Bit-Line Shielding Method for Ferroelectric Memories
Patent:
6,717,839 →
Application:
10/404,941 →
Ferroelectric Non-Volatile Logic Elements
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Corrective Assignment to Correct the 8647899 Previously Recorded on Reel 035240 Frame 0429. Assignor(S) Hereby Confirms the Security Interst.
Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →