Granted Patent B2

US 6,894,549 · App. 10/613,427 · Granted May 17, 2005

Abstract

Claims (252)

1. A ferroelectric, non-volatile SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output; and

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and

wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground; and a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

2. The SR flip-flop of claim 1 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

3. The SR flip-flop of claim 1 further comprising a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

4. The SR flip-flop of claim 1 further comprising a precharge circuit coupled to the first and second NAND gates.

5. The SR flip-flop of claim 1 further comprising an equalization circuit coupled to the first and second NAND gates.

6 .The SR flip-flop of claim 1 further comprising a gate control circuit coupled to the first and second NAND gates.

7. The SR flip-flop of claim 1 in which the first and second NAND gates further comprise an internal drive isolation circuit.

8. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to th Q output; and

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and

wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground, and third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

9. The SR flip-flop of claim 8 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

10. The SR flip-flop of claim 8 further comprising a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

11. The SR flip-flop of claim 8 further comprising a precharge circuit coupled to the first and second NAND gates.

12. The SR flip-flop of claim 8 further comprising an equalization circuit coupled to the first 8 and second NAND gates.

13 .The SR flip-flop of claim 8 further comprising a gate control circuit coupled to the first and second NAND gates.

14. The SR flip-flop of claim 8 in which the first and second NAND gates further comprise an internal drive isolation circuit.

15. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs; and

means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

16. The SR flip-flop of claim 15 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

17. The SR flip-flop of claim 15 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

18. The SR flip-flop of claim 15 further comprising a precharge circuit coupled to the first and second NAND gates.

19. The SR flip-flop of claim 15 further comprising an equalization circuit coupled to the first and second NAND gates.

20. The SR flip-flop of claim 15 further comprising a gate control circuit coupled to the first and second NAND gates.

21. The SR flip-flop of claim 15 in which the first and second NAND gates further comprise an internal drive isolation circuit.

22. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs; and

a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

23. The SR flip-flop of claim 22 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

24. The SR flip-flop of claim 22 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

25. The SR flip-flop of claim 22 further comprising a precharge circuit coupled to the first and second NAND gates.

26. The SR flip-flop of claim 22 further comprising an equalization circuit coupled to the first and second NAND gates.

27. The SR flip-flop of claim 22 further comprising a gate control circuit coupled to the first and second NAND gates.

28. The SR flip-flop of claim 22 in which the first and second NAND gates further comprise an internal drive isolation circuit.

29. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NAND gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NAND gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output; and

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and

wherein the first and second NAND gates further comprise an internal drive isolation circuit.

30. The SR flip-flop of claim 29 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

31. The SR flip-flop of claim 29 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

32. The SR flip-flop of claim 29 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

33. The SR flip-flop of claim 29 further comprising a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

34. The SR flip-flop of claim 29 further comprising a precharge circuit coupled to the first and second NAND gates.

35. The SR flip-flop of claim 29 further comprising an equalization circuit coupled to the first and second NAND gates.

36. The SR flip-flop of claim 29 further comprising a gate control circuit coupled to the first and second NAND gates.

37. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output; and

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and

wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground; and a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

38. The SR flip-flop of claim 37 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

39. The SR flip-flop of claim 37 further comprising a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

40. The SR flip-flop of claim 37 further comprising a precharge circuit coupled to the first and second NOR gates.

41. The SR flip-flop of claim 37 further comprising an equalization circuit coupled to the first and second NOR gates.

42. The SR flip-flop of claim 37 further comprising a gate control circuit coupled to the first and second NOR gates.

43. The SR flip-flop of claim 37 in which the first and second NOR gates further comprise an internal drive isolation circuit.

44. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output; and

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and

wherein the ferroelectric capacitor circuit comprises a first ferroelectric capacitor coupled between the Q output and ground, a second ferroelectric capacitor coupled between the complementary Q output and ground, and third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

45. The SR flip-flop of claim 44 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

46. The SR flip-flop of claim 44 further comprising a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

47. The SR flip-flop of claim 44 further comprising a precharge circuit coupled to the first and second NOR gates.

48. The SR flip-flop of claim 44 further comprising an equalization circuit coupled to the first and second NOR gates.

49. The SR flip-flop of claim 44 further comprising a gate control circuit coupled to the first and second NOR gates.

50. The SR flip-flop of claim 44 in which the first and second NAND gates further comprise an internal drive isolation circuit.

51. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs; and

means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

52. The SR flip-flop of claim 51 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

53. The SR flip-flop of claim 51 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

54. The SR flip-flop of claim 51 further comprising a precharge circuit coupled to the first and second NOR gates.

55. The SR flip-flop of claim 51 further comprising an equalization circuit coupled to the first and second NOR gates.

56. The SR flip-flop of claim 51 further comprising a gate control circuit coupled to the first and second NOR gates.

57. The SR flip-flop of claim 51 in which the first and second NOR gates further comprise an internal drive isolation circuit.

58. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input; a reset input;

a Q output;

a complementary Q output;

a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs; and

a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

59. The SR flip-flop of claim 58 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q

output and ground; and

a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

60. The SR flip-flop of claim 58 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

61. The SR flip-flop of claim 58 further comprising a precharge circuit coupled to the first and second NOR gates.

62. The SR flip-flop of claim 58 further comprising an equalization circuit coupled to the first and second NOR gates.

63. The SR flip-flop of claim 58 further comprising a gate control circuit coupled to the first and second NOR gates.

64. The SR flip-flop of claim 58 in which the first and second NOR gates further comprise an internal drive isolation circuit.

65. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first NOR gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second NOR gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output; and

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs, and

wherein the first and second NOR gates further comprise an internal drive isolation circuit.

66. The SR flip-flop of claim 65 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

a third ferroelectric capacitor coupled between the Q and complementary Q outputs.

67. The SR flip-flop of claim 65 in which the ferroelectric capacitor circuit comprises:

a first ferroelectric capacitor coupled between the Q output and ground;

a second ferroelectric capacitor coupled between the complementary Q output and ground; and

third and fourth serially-coupled matched ferroelectric capacitors coupled between the Q and complementary Q outputs.

68. The SR flip-flop of claim 65 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

69. The SR flip-flop of claim 65 further comprising a pass gate circuit for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

70. The SR flip-flop of claim 70 further comprising a precharge circuit coupled to the first and second NOR gates.

71. The SR flip-flop of claim 65 further comprising an equalization circuit coupled to the first and second NOR gates.

72. The SR flip-flop of claim 65 further comprising a gate control circuit coupled to the first and second NOR gates.

73. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first logic gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second logic gate having a first input coupled to the reset input, a second output;

a ferroelectric capacitor circuit comprising first, second, and third ferroelectric capacitors, including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;

a J input;

a K input;

a first NAND gate having a first input coupled to the Q output of the SR flip-flop, a second input coupled to the K input, a third input for receiving a clock signal and an output coupled to the set input of the SR flip-flop; and

a second NAND gate having a first input for receiving the clock signal, a second input coupled to the J input, a third input coupled to the complementary Q output of the SR flip-flop and an output coupled to the reset input of the SR flip-flop.

74. The SR flip-flop of claim 73 further comprising a first controlled power supply coupled to the SR flip-flop.

75. The SR flip-flop of claim further comprising a second controlled power supply coupled to the SR flip-flop.

76. The SR flip-flop of claim 73 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

77. The SR flip-flop of claim 73 further comprising a precharge circuit coupled to the SR flip-flop.

78. The SR flip-flop of claim 73 further comprising an equalization circuit coupled to the SR flip-flop.

79. The SR flip-flop of claim 73 further comprising a gate control circuit coupled to the SR flip-flop.

80. The SR flip-flop of claim 73 in which the SR flip-flop further comprises an internal drive isolation circuit.

81. The SR flip-flop of claim 73 further comprising:

a slave JK flip-flop interposed between the Q output and the complementary Q output, and the first input of the first NAND gate and the third input of the second NAND gate.

82. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first logic gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second logic gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;

a J input;

a K input:

a first NAND gate having a first input coupled to the Q output of the SR flip-flop, a second input coupled to the K input, a third input for receiving a clock signal and an output coupled to the set input of the SR flip-flop; and

a second NAND gate having a first input for receiving the clock signal, a second input coupled to the J input, a third input coupled to the complementary Q output of the SR flip-flop and an output coupled to the reset input of the SR flip-flop,

wherein the SR flip-flop further comprises an internal drive isolation circuit.

83. The SR flip-flop of claim 82 further comprising a first second controlled power supply coupled to the SR flip-flop.

84. The SR flip-flop of claim 83 further comprising a second controlled power supply coupled to the SR flip-flop.

85. The SR flip-flop of claim 84 which the ferroelectric capacitor circuit comprises first, second, and third ferroelectric capacitors.

86. The SR flip-flop of claim 82 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

87. The SR flip-flop of claim 82 further comprising a precharge circuit coupled to the SR flip-flop.

88. The SR flip-flop of claim 82 further comprising an equalization circuit coupled to the SR flip-flop.

89. The SR flip-flop of claim 82 further comprising a gate control circuit coupled to the SR flip-flop.

90. The SR flip-flop of claim 82 further comprising:

a slave JK flip-flop interposed between the Q output and the complementary Q output, and the first input of the first NAND gate and the third input of the second NAND gate.

91. A ferroelectric, non-volatile, SR flip-flop comprising:

a set input;

a reset input;

a Q output;

a complementary Q output;

a first logic gate having a first input coupled to the set input, a second input coupled to the Q output, and an output coupled to the complementary Q output;

a second logic gate having a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output;

a ferroelectric capacitor circuit including at least one ferroelectric load capacitor and at least one ferroelectric storage capacitor coupled to the Q and complementary Q outputs;

a J input;

a K input;

a first NAND gate having a first input coupled to the Q output of the SR flip-flop, a second input coupled to the K input, a third input for receiving a clock signal and an output coupled to the set input of the SR flip-flop;

a second NAND gate having a first input for receiving the clock signal, a second input coupled to the J input, a third input coupled to the complementary Q output of the SR flip-flop and an output coupled to the reset input of the SR flip-flop; and

a slave JK flip-flop interposed between the Q output and the complementary Q output, and the first input of the first NAND gate and the third input of the second NAND gate.

92. The SR flip-flop of claim 91 further comprising a first controlled power supply coupled to the SR flip-flop.

93. The SR flip-flop of claim 92 further comprising a second controlled power supply coupled to the SR flip-flop.

94. The SR flip-flop of claim 91 in which the ferroelectric capacitor circuit comprises first, second, and third ferroelectric capacitors.

95. The SR flip-flop of claim 91 further comprising means for selectively coupling the ferroelectric capacitor circuit to the Q and complementary Q outputs.

96. The SR flip-flop of claim 91 further comprising a precharge circuit coupled to the SR flip-flop.

97. The SR flip-flop of claim 91 further comprising an equalization circuit coupled to the SR flip-flop.

98. The SR flip-flop of claim 91 further comprising a gate control circuit coupled to the SR flip-flop.

99. The SR flip-flop of claim 91 in which the SR flip-flop further comprises an internal drive isolation circuit.

Assignments (8)