IP Library Assignment 049746/0970
Patent Assignment
Reel/Frame 049746/0970

Assignment of Assignor's Interest

Recorded: 2019-07-14 Pages: 11
Assignor
POWERCHIP TECHNOLOGY CORPORATION
Executed: 2019-06-28
Assignee
POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
NO. 18, LI-HSIN RD. 1, HSINCHU SCIENCE PARK,, HSINCHU, TAIWAN
Covered Properties (20)
Nand Flash Memory Cell Row
Patent: 7,005,699 →
Application: 10/707,826 →
Publication: US 2005/0087794
Method of Building a Defect Database
Patent: 7,020,536 →
Application: 10/708,059 →
Publication: US 2005/0177264
Semiconductor Process and Yield Analysis Integrated Real-Time Management Method
Patent: 7,099,729 →
Application: 10/708,277 →
Publication: US 2005/0187648
[Method of Forming Floating Gate of Memory Device]
Patent: 6,812,120 →
Application: 10/708,351 →
Method and Related System for Semiconductor Equipment Prevention Maintenance Management
Patent: 6,950,783 →
Application: 10/708,572 →
Publication: US 2005/0203858
Method and Related System for Semiconductor Equipment Early Warning Management
Patent: 6,999,897 →
Application: 10/708,573 →
Publication: US 2005/0203715
Method of Fabricating Non-Volatile Memory Cell Adapted for Integration of Devices and for Multiple Read/Write Operations
Patent: 7,049,189 →
Application: 10/708,904 →
Publication: US 2005/0176203
Aseismatic Device
Patent: 7,028,433 →
Application: 10/708,944 →
Publication: US 2005/0126423
[Split Gate Flash Memory Cell and Manufacutirng Method Thereof]
Patent: 6,821,849 →
Application: 10/709,309 →
Publication: US 2004/0197999
[Flash Memory with Self-Aligned Split Gate and Methods for Fabricating and for Operating the Same]
Patent: 6,838,343 →
Application: 10/709,310 →
Publication: US 2004/0196720
Tool for Removing Particles from Reticle
Patent: 7,234,196 →
Application: 10/709,335 →
Publication: US 2005/0168739
[Non-Volatile Memory Cell and Manufacturing Method Thereof]
Patent: 7,038,267 →
Application: 10/709,372 →
Publication: US 2005/0145921
[Method of Fabricating Flash Memory Cell]
Patent: 6,972,260 →
Application: 10/709,469 →
Publication: US 2005/0250335
[Flash Memory Structure and Operating Method Thereof]
Patent: 6,914,826 →
Application: 10/709,507 →
Publication: US 2004/0217412
Method of Forming Barrier Layer
Patent: 7,115,214 →
Application: 10/709,552 →
Publication: US 2005/0103750
[Flash Memory Device Structure and Manufacturing Method Thereof]
Patent: 6,913,974 →
Application: 10/709,590 →
Publication: US 2004/0197994
[Pipe Trap]
Patent: 7,344,579 →
Application: 10/709,607 →
Publication: US 2005/0144915
[Method of Fabricating a Flash Memory]
Patent: 6,893,918 →
Application: 10/709,639 →
[Method of Fabricating a Flash Memory]
Patent: 6,984,559 →
Application: 10/709,640 →
Publication: US 2005/0176200
Structure, Fabrication Method and Operating Method for Flash Memory
Patent: 6,834,011 →
Application: 10/829,414 →
Publication: US 2004/0196714
Related Assignments (2)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name Jun 24, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049562/0151 →
Change of Name Jun 24, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049562/0154 →