IP Library Assignment 049562/0151
Patent Assignment
Reel/Frame 049562/0151

Change of Name

Recorded: 2019-06-24 Pages: 3
Assignor
POWERCHIP SEMICONDUCTOR CORP.
Executed: 2010-08-09
Assignee
POWERCHIP TECHNOLOGY CORPORATION
NO. 12, LI-HSIN ROAD I, HSINCHU SCIENCE PARK,, HSINCHU, TAIWAN
Covered Properties (20)
[Sputtering Apparatus and Manufacturing Method of Metal Layer/Metal Compound Layer by Using Thereof]
Patent: 6,811,662 →
Application: 10/604,857 →
[Flash Memory Cell and Fabricating Method Thereof]
Patent: 6,815,758 →
Application: 10/604,861 →
Re-Performable Spin-on Process
Patent: 6,881,590 →
Application: 10/604,895 →
Publication: US 2005/0048760
Method for Analyzing Final Test Parameters
Patent: 6,898,539 →
Application: 10/604,979 →
Publication: US 2004/0138856
[Split Gate Flash Memory Cell and Manufacturing Method Thereof]
Patent: 6,897,521 →
Application: 10/605,198 →
Publication: US 2005/0006691
[Method for Detecting Defect of Semiconductor Device]
Patent: 6,806,104 →
Application: 10/605,357 →
Flash Memory Cell Structure
Patent: 6,963,105 →
Application: 10/605,419 →
Publication: US 2004/0145006
Single-Poly Eprom and Method for Forming the Same
Patent: 6,917,070 →
Application: 10/663,177 →
Publication: US 2004/0053467
Dual-Bit Nitride Read Only Memory Cell with Parasitic Amplifier and Methods of Fabricating and Reading the Same
Patent: 6,757,208 →
Application: 10/665,599 →
Method for Manufacturing Non-Volatile Memory Cell
Patent: 6,869,842 →
Application: 10/707,418 →
Publication: US 2004/0229436
Wafer Grinding Apparatus
Patent: 6,910,956 →
Application: 10/707,561 →
Publication: US 2005/0136809
Management System of Monitor Wafers
Patent: 6,865,434 →
Application: 10/707,626 →
Publication: US 2005/0038544
Fabrication Method of a Flash Memory Device
Patent: 6,855,599 →
Application: 10/707,668 →
Publication: US 2004/0121536
[Multi-Level Memory Cell]
Patent: 7,164,177 →
Application: 10/707,677 →
Publication: US 2005/0145919
[Non-Volatile Memory Device and Method of Manufacturing the Same]
Patent: 7,091,550 →
Application: 10/707,704 →
Publication: US 2005/0082600
Method of Defect Review
Patent: 7,071,011 →
Application: 10/707,824 →
Publication: US 2005/0159909
Nand Flash Memory Cell Row
Patent: 7,005,699 →
Application: 10/707,826 →
Publication: US 2005/0087794
Method of Building a Defect Database
Patent: 7,020,536 →
Application: 10/708,059 →
Publication: US 2005/0177264
Semiconductor Process and Yield Analysis Integrated Real-Time Management Method
Patent: 7,099,729 →
Application: 10/708,277 →
Publication: US 2005/0187648
[Method of Forming Floating Gate of Memory Device]
Patent: 6,812,120 →
Application: 10/708,351 →
Related Assignments (5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 12, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049732/0132 →
Assignment of Assignor's Interest Jul 12, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049732/0147 →
Assignment of Assignor's Interest Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049746/0970 →
Assignment of Assignor's Interest Apr 8, 2020
From: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 052337/0735 →
Assignment of Assignor's Interest Sep 7, 2020
From: POWERCHIP TECHNOLOGY CORPORATION
To: NEXCHIP SEMICONDUCTOR CORPORATION
Reel/Frame 053704/0522 →