Sense amplifier with bit line pre-charge circuit for reading flash memory cells in an array
View Patent ↗The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre-charge circuit for pre-charging a bit line during a pre-charge period to increase the speed of read operations. In another embodiment, a sense amplifier comprises simplified address decoding circuitry to increase the speed of read operations.
1. A sensing circuit for reading a selected flash memory cell in a first array of flash memory cells or in a second array of flash memory cells, comprising:
a first circuit coupled to a first bit line in the first array;
a second circuit coupled to a second bit line in the second array;
a comparator comprising a first input coupled to a first node in the first circuit and a second input coupled to a second node the second circuit, an output of the comparator coupled to a first set of inverters and to a second set of inverters in parallel to the first set of inverters, the first set of inverters comprising an odd number of inverters and the second set of inverters comprising an even number of inverters;
a multiplexer comprising a first input for receiving an output of the first set of inverters and a second input for receiving an output of the second set of inverters, the multiplexer controlled by a select signal to output a signal indicative of the data stored in the selected flash memory cell;
wherein the select signal is set to a first state or a second state, the first state indicating that the first bit line is coupled to the selected flash memory cell and the second bit line is a reference bit line and the second state indicating that the first bit line is a reference bit line and the second bit line is coupled to the selected flash memory cell.
2. The sensing circuit of claim 1 , further comprising:
a pre-charge circuit coupled to the first node and the second node to charge the first node and the second node to a predetermined voltage prior to a read operation.
3. The sensing circuit of claim 1 , wherein the first circuit comprises a first PMOS transistor and the second circuit comprises a second PMOS transistor, wherein the first PMOS and second PMOS transistor are symmetrical.
4. The sensing circuit of claim 3 , wherein the first PMOS and second PMOS transistor are activated during a read operation.
5. A sensing circuit for reading a selected flash memory cell in a first array of flash memory cells, comprising:
a first circuit coupled to a first bit line in the first array;
a second circuit coupled to a second bit line in a second array of flash memory cells; and
a comparator comprising a first input coupled to a first node in the first circuit and a second input coupled to a second node the second circuit, an output of the comparator indicating the value stored in the selected flash memory cell;
wherein the first circuit comprises circuitry for pulling the first bit line to ground and pre-charging the first node to a predetermined voltage during a pre-charge period, and the second circuit comprises circuitry for pulling the second bit line to ground and pre-charging the second node to the predetermined voltage during the pre-charge period.
6. The sensing circuit of claim 5 , wherein the first circuit further comprises for pre-charging the first bit line and the first node to the predetermined voltage during a read active mode, and the second circuit comprises circuitry for pre-charging the second bit lint and the second node to the predetermined voltage during the read active mode.