Systems and methods to avoid over programming at infrequent smart verify acquisition for high-performance 3D NAND
A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.
1 . A method of programming a memory device, comprising the steps of:
performing a smart verify operation to acquire an initial programming voltage;
performing a program operation on a selected wordline starting with the initial programming voltage;
performing a bitscan operation of a highest state being verified;
based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines; and
in response to the result of the bitscan operation failing, reducing a value of the initial programming voltage for programming of subsequent wordlines.
2 . The method as set forth in claim 1 , further including the step of:
in response to the result of the bitscan operation passing, maintaining a value of the initial programming voltage for programming of subsequent wordlines.
3 . The method as set forth in claim 1 , further including the step of:
in response to the result of the bitscan operation failing, determining if the highest state is of an ‘S 1 ’ data state and if a current program loop is a first loop of a plurality of program loops of the program operation;
in response to determining that the highest state is of the ‘S 1 ’ data state and the current program loop is the first loop, reducing a value of the initial programming voltage for programming of subsequent wordlines.
4 . The method as set forth in claim 1 , further including the step of:
based on a number of high threshold bit fails, reducing a value of the initial programming voltage for programming of subsequent wordlines.
5 . The method as set forth in claim 1 , further including the step of:
based on a number of high threshold bit fails, initiating a verify of a next data state in a next program loop of a plurality of program loops of the program operation.
6 . A method of programming a memory device, comprising the steps of:
performing a smart verify operation to acquire an initial programming voltage;
performing a program operation on a selected wordline starting with the initial programming voltage;
performing a bitscan operation of a highest state being verified;
based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines; and
in response to the result of the bitscan operation failing, initiating a verify of a next data state in a next program loop of a plurality of program loops of the program operation.
7 . A memory device, comprising:
at least one memory block that includes a plurality of memory cells arranged in a plurality of word lines;
control circuitry configured to program the memory cells of the at least one memory block in a plurality of program loops, the control circuitry being configured to:
perform a smart verify operation to acquire an initial programming voltage;
perform a program operation on a selected wordline starting with the initial programming voltage;
perform a bitscan operation of a highest state being verified;
based on a result of the bitscan operation, adjust the initial programming voltage for programming of subsequent wordlines; and
in response to the result of the bitscan operation being failing, reduce a value of the initial programming voltage for programming of subsequent wordlines.
8 . The memory device as set forth in claim 7 , wherein the control circuitry is further configured to:
in response to the result of the bitscan operation being failing, initiate a verify of a next data state in a next program loop of a plurality of program loops of the program operation.
9 . The memory device as set forth in claim 7 , wherein the control circuitry is further configured to:
in response to the result of the bitscan operation being passing, maintain a value of the initial programming voltage for programming of subsequent wordlines.
10 . The memory device as set forth in claim 7 , wherein the control circuitry is further configured to:
in response to the result of the bitscan operation being failing, determine if the highest state is of an ‘S 1 ’ data state and if a current program loop is a first loop of a plurality of program loops of the program operation;
in response to determining that the highest state is of the ‘S 1 ’ data state and the current program loop is the first loop, reduce a value of the initial programming voltage for programming of subsequent wordlines.
11 . The memory device as set forth in claim 7 , wherein the control circuitry is further configured to:
based on a number of high threshold bit fails, reduce a value of the initial programming voltage for programming of subsequent wordlines.
12 . The memory device as set forth in claim 7 , wherein the control circuitry is further configured to:
based on a number of high threshold bit fails, initiate a verify of a next data state in a next program loop of a plurality of program loops of the program operation.
13 . An apparatus, comprising:
at least one memory block that includes a plurality of memory cells arranged in a plurality of word lines;
a programming means for programming user data into the plurality of memory cells and configured to program the memory cells of the at least one memory block in a plurality of program loops, the programming means being configured to:
perform a smart verify operation to acquire an initial programming voltage;
perform a program operation on a selected wordline starting with the initial programming voltage;
perform a bitscan operation of a highest state being verified;
based on a result of the bitscan operation, adjust the initial programming voltage for programming of subsequent wordlines; and
in response to the result of the bitscan operation failing, reduce a value of the initial programming voltage for programming of subsequent wordlines.
14 . The apparatus as set forth in claim 13 , wherein the control circuitry is further configured to:
in response to the result of the bitscan operation failing, initiate a verify of a next data state in a next program loop of a plurality of program loops of the program operation.
15 . The apparatus as set forth in claim 13 , wherein the control circuitry is further configured to:
in response to the result of the bitscan operation passing, maintain a value of the initial programming voltage for programming of subsequent wordlines.
16 . The apparatus as set forth in claim 13 , wherein the control circuitry is further configured to:
in response to the result of the bitscan operation failing, determine if the highest state is of an ‘S 1 ’ data state and if a current program loop is a first loop of a plurality of program loops of the program operation;
in response to determining that the highest state is of the ‘S 1 ’ data state and the current program loop is the first loop, reduce a value of the initial programming voltage for programming of subsequent wordlines.
17 . The apparatus as set forth in claim 13 , wherein the control circuitry is further configured to:
based on a number of high threshold bit fails, reduce a value of the initial programming voltage for programming of subsequent wordlines.