Reduced size split gate non-volatile flash memory cell and method of making same
View Patent ↗A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.
1. A method of forming a non-volatile memory cell array comprising:
forming a layer of first insulation material on a semiconductor substrate;
forming a plurality of first trenches in the layer of first insulation material that extend in a first direction;
filling the plurality of first trenches with a second insulation material different than the first insulation material;
forming a plurality of second trenches in the layer of first insulation material that extend in a second direction orthogonal to the first direction;
extending the plurality of second trenches into the substrate;
filling the plurality of second trenches with a third insulation material, wherein the third insulation material defines parallel isolation regions in the semiconductor substrate with an active region between each adjacent pair of the isolation regions, and wherein the isolation regions are not formed in the substrate under the plurality of first trenches;
removing the second insulation material;
forming a plurality of parallel, continuous source line diffusions in the semiconductor substrate by performing an implantation into the first trenches, wherein each source line diffusion extends in the first direction and across each of the active regions;
forming a plurality of memory cell pairs in each of the active regions, wherein each of the memory cell pairs includes:
a source region in the substrate which is a portion of one of the continuous source line diffusions,
first and second drain regions in the substrate, wherein a first channel region extends between the first drain region and the source region and a second channel region extends between the second drain region and the source region,
a first floating gate disposed over and insulated from a first portion of the first channel region,
a second floating gate disposed over and insulated from a first portion of the second channel region,
a first select gate disposed over and insulated from a second portion of the first channel region,
a second select gate disposed over and insulated from a second portion of the second channel region,
a first control gate disposed over and insulated from the first floating gate,
a second control gate disposed over and insulated from the second floating gate, and
an erase gate disposed over and insulated from the source region.
2. The method of claim 1 , further comprising:
forming a layer of fourth insulation material directly on a surface of the semiconductor substrate, wherein the layer of first insulation material is formed directly on the layer of fourth insulation material.
3. The method of claim 1 , wherein:
the first insulation material is nitride;
the second insulation material is oxide; and
the third insulation material is oxide.