Copper to aluminum interlayer interconnect using stud and via liner
View Patent ↗Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.
1. An integrated circuit including
a patterned copper layer,
a patterned aluminum layer,
an opening in a layer of material, said opening extending between a location on said patterned copper layer and a location on said patterned aluminum layer,
a multi-layer barrier liner in said opening and having a thickness, said barrier liner extending between said patterned aluminum layer and said patterned copper layer at said location on said patterned copper layer and across said copper layer to cover a bottom of said opening, said multi-layer barrier layer including at least a first layer being of a material which is conductive and having adhesion to copper and tungsten comparable to that of tantalum or tantalum nitride or titanium nitride and resisting interdiffusion of copper and tungsten and a second layer formed on said first layer and being of a material which assists in the formation of a stud during deposition of tungsten on which tungsten can be deposited, one or both of said first and second layers forming a conductive barrier to process materials which are reactive with copper, and
a stud connection formed of tungsten and located within said barrier liner wherein said barrier liner comprises
a layer of tantalum nitride, and
a layer of PVD tungsten.
2. An integrated circuit including
a patterned copper layer,
a patterned aluminum layer,
an opening in a layer of material, said opening extending between a location on said patterned copper layer and a location on said patterned aluminum layer,
a multi-layer barrier liner in said opening and having a thickness, said barrier liner extending between said patterned aluminum layer and said patterned copper layer at said location on said patterned copper layer and across said copper layer to cover a bottom of said opening, said multi-layer barrier layer including at least a first layer being of a material which is conductive and having adhesion to copper and tungsten comparable to that of tantalum or tantalum nitride or titanium nitride and resisting interdiffusion of copper and tungsten and a second layer formed on said first layer and being of a material which assists in the formation of a stud during deposition of tungsten on which tungsten can be deposited, one or both of said first and second layers forming a conductive barrier to process materials which are reactive with copper, and
a stud connection formed of tungsten and located within said barrier liner wherein said barrier liner comprises
a layer of tantalum nitride,
a layer of titanium nitride, and
a layer of titanium nitride or PVD tungsten.
3. An integrated circuit as recited in claim 1 wherein said patterned aluminum layer includes a layer of at least one of titanium and titanium nitride.
4. An integrated circuit as recited in claim 2 wherein said patterned aluminum layer includes a layer of at least one of titanium and titanium nitride.
5. An integrated circuit as recited in claim 1 , further including a covering layer.
6. An integrated circuit as recited in claim 3 wherein said covering layer includes a layer of silane-based high density plasma oxide.
7. An integrated circuit as recited in claim 2 , further including a covering layer.
8. An integrated circuit as recited in claim 7 wherein said covering layer includes a layer of silane-based high density plasma oxide.