Tileable field-programmable gate array architecture
View Patent ↗A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks, defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks, determining an expected logic result for a selected logical combination of the individual test inputs, applying the individual test inputs to the first end of each of the at least two of the first sets of tracks, performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result, and flagging an error if the actual result is not identical with the expected logic result.
1. A method for testing a routing circuitry in a field programmable gate array (FPGA) having a first FPGA tile, the routing circuitry having a plurality of first sets of tracks running in a first direction, each first set of tracks having a plurality of individual track segments that are programmably connectable to one another between a first end and a second end by individual programmable elements, the method comprising:
providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks;
defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks;
determining an expected logic result for a selected logical combination of the individual test inputs to the at least two of the first sets of tracks;
applying the individual test inputs to the first end of each of the at least two of the first sets of tracks;
performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result; and
flagging an error if the actual result is not identical with the expected logic result.
2. The method of claim 1 wherein the at least two of the first sets of tracks are a pair of adjacent first sets of tracks.
3. The method of claim 2 wherein the individual test inputs applied to the first ends of the pair of adjacent first sets of tracks are opposite logic states.
4. The method of claim 1 wherein the at least two of the first sets of tracks are a plurality of pairs of adjacent first sets of tracks.
5. The method of claim 4 wherein the individual test inputs applied to the first ends of the plurality of pairs of adjacent first sets of tracks are alternating logic states.
6. The method of claim 5 wherein:
the second ends of odd ones of the plurality of pairs of adjacent first sets of tracks are coupled to inputs of a first wired-NOR circuit having an output and to inputs of a first wired-NAND circuit having an output; and
the second ends of even ones of the plurality of pairs of adjacent first sets of tracks are coupled to inputs of a second wired-NOR circuit having an output and to inputs of a second wired-NAND circuit having an output.
7. The method of claim 5 wherein:
the second ends of odd ones of the plurality of pairs of adjacent second sets of tracks are coupled to inputs of a third wired-NOR circuit having an output and to inputs of a third wired-NAND circuit having an output; and
the second ends of even ones of the plurality of pairs of adjacent second sets of tracks are coupled to inputs of a fourth wired-NOR circuit having an output and to inputs of a fourth wired-NAND circuit having an output.
8. The method of claim 1 wherein the first direction is a vertical direction.
9. The method of claim 1 wherein the routing circuitry also has a plurality of second sets of tracks running in a second direction orthogonal to the first direction, each second set of tracks having a plurality of individual track segments that are programmably connectable to one another between a first end and a second end by individual programmable elements, the method further comprising:
providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the second sets of tracks;
defining individual test inputs to apply to the first end of each of the at least two of the second sets of tracks;
determining an expected logic result for a selected logical combination of the individual test inputs to the at least two of the second set of tracks;
applying the individual test inputs to the first end of each of the at least two of the second sets of tracks;
performing the selected logical combination on the second ends of the at least two of the second sets of tracks to generate an actual logic result from the at least two of the second sets of tracks; and
flagging an error if the actual result from the at least two of the second sets of tracks is not identical with the expected logic result.
10. The method of claim 9 wherein the at least two of the second sets of tracks are a pair of adjacent second sets of tracks.
11. The method of claim 10 wherein the individual test inputs applied to the first ends of the pair of adjacent second sets of tracks are opposite logic states.
12. The method of claim 9 wherein the at least two of the second sets of tracks are a plurality of pairs of adjacent second sets of tracks.
13. The method of claim 12 wherein the individual test inputs applied to the first ends of the plurality of pairs of adjacent second sets of tracks are alternating logic states.