Granted Patent
Utility
US 6,518,835
· Confirmation No. 3202
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING AN OPTIMAL CIRCUIT LAYOUT TO ENSURE STABILIZATION OF INTERNAL SOURCE VOLTAGES WITHOUT LOWERING CIRCUIT FUNCTIONS AND/OR OPERATING PERFORMANCE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-05-13 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-05-13 | A.PE |
Preliminary Amendment | 73 | View | |
| 2002-05-13 | SPEC |
Specification | 49 | View | |
| 2002-05-13 | CLM |
Claims | 9 | View | |
| 2002-05-13 | ABST |
Abstract | 1 | View | |
| 2002-05-13 | DRW |
Drawings-only black and white line drawings | 7 | View | |
| 2002-05-13 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Yoshiro Riho
Tokyo, JAPAN
Kiyoshi Nakai
Tokyo, JAPAN
Hidekazu Egawa
Tokyo, JAPAN
Yukihide Suzuki
Tokyo, JAPAN
Isamu Fujii
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
327/565
H10W20/495
G11C11/407
H10W72/00
H10W20/496
Prosecution
- Examiner
- WELLS, KENNETH B
- Art Unit
- 2816
- Customer No.
- 20457
- Docket No.
- 501.37402CX1
- Confirmation No.
- 3202
Foreign Priority
10-241607
·
1998-08-27
·
JAPAN
Publication
- Pub. No.
- US20020130714A1
- Pub. Date
- 2002-09-19
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2009-06-10
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Quick Facts
- Patent No.
- US 6,518,835
- App. No.
- 10/142,897
- Filed
- 2002-05-13
- Granted
- 2003-02-11
- Pub. No.
- US20020130714A1
- Examiner
- WELLS, KENNETH B
- Art Unit
- 2816
- PTA
- 0 days
External Links