Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers

1. Circuitry for providing low voltage differential signaling for a field programmable gate array (FPGA) comprising:

a first output buffer;

a second output buffer;

a first output line;

a second output line;

a delay circuit connected to said first output line;

an inverter connected to said first output line;

a first multiplexer having a first input connected to an output of said delay circuit, a second input connected to said first outline and an output connected to said first output buffer, wherein said first multiplexer selectively connects said first output line and a delayed signal from said first output line to said first output buffer;

a second multiplexer having a first input connected to an output of said inverter to receive an inverted signal from said first output line, a second input connected to said second input line and an output connected to said second output buffer; and

control circuitry connected to said first multiplexer and said second multiplexer to determine a signal connected to said first output buffer by said first multiplexer and a signal connected to said second output buffer by said second output multiplexer.

2. The circuitry of claim 1 wherein said control circuitry signals said first multiplexer to connect said delay circuit to said first output buffer and said second multiplexer to connect said inverter of said first output signal said second output buffer to provide low voltage differential signaling.

3. The circuitry of claim 1 wherein said control circuitry signals said first multiplexer to connect first output line to said first output buffer and said second multiplexer to connect said second output line to said second output buffer to allow said first input buffer and said second input buffer to operate independently.

4. A method of forming an low voltage differential signaling comprising:

delaying a first output signal;

selecting between said first output signal and said delayed first output signal to provide to a first output buffer;

inverting said first output signal;

selecting between said inverted first output signal and a second output signal to provide to a second output buffer.

5. The method of claim 4 wherein said delayed first output signal and said inverted first output signal are selected to provide low voltage differential signaling.

6. The method of claim 4 wherein said first output signal and said second output signal are selected to allow said first output buffer and said second output buffer to operate independently.