Granted Patent B1

US 6,859,748 · App. 10/190,420 · Granted Feb 22, 2005

Abstract

Claims (54)

1. A method of evaluating an integrated circuit fabrication process comprising:

performing an electrical test on a test structure comprising a first region having a polygon cross-section;

measuring a parameter of said electrical test performed on said test structure;

performing said electrical test on a control test structure comprising a second region having a circular cross section, wherein a perimeter of said circular cross section is substantially equal to a perimeter of said polygon cross-section;

measuring said parameter of said electrical test performed on said control test structure;

determining a corner effect on said parameter as a function of the difference between said measured parameter of said electric test performed on said test structure and said measured parameter of said electrical test performed on said control test structure.

2. The method according to claim 1 , wherein said parameter is selected from a group consisting of silicon stress, crystal imperfection, crystalline dislocation, oxide layer imperfection.

3. The method according to claim 1 , wherein said electrical test comprises a capacitance-voltage test.

4. The method according to claim 1 , wherein said electrical test comprises a current injection test.

5. The method according to claim 1 , wherein:

said first region comprises an isolation region; and

said second region comprises an isolation region.

6. The method according to claim 1 , wherein:

said first region comprises a device region; and

said second region comprises a device region.

7. An apparatus for evaluating a memory device comprising:

a means for performing various electrical tests upon a test structure, wherein said test structure comprises a plurality of regions having edges and corners;

means for collecting a first set of values regarding said various electrical tests conducted on said test structure;

a means for performing various electrical tests upon a control test structure, wherein said control test structure comprises a plurality of regions having an edge and no corners and having a perimeter substantially equal or analogous to a perimeter of said test structure;

means for collecting a second set of values regarding said various electrical tests conducted on said control test structure; and

a means for generating data regarding a difference between said first set of values and said second set of values.

8. The apparatus according to claim 7 , wherein said first and second set of values comprise capacitance-voltage values, current injection values and current-voltage values.

9. The apparatus according to claim 7 , wherein said plurality of regions comprise shallow trench isolation regions.

10. The apparatus according to claim 7 , wherein said plurality of regions comprise device regions.

11. The apparatus according to claim 7 , further comprising a means for storing said first set of values and said second set of values.

12. The apparatus according to claim 7 , further comprising a means for storing said data.

13. An apparatus for evaluating a memory device fabrication process comprising:

a test structure comprising an array of first regions, each having a corner, formed in a second region;

a control test structure comprising an array of third regions, each not having said corner, formed in a forth region, wherein a perimeter of said array of third regions are substantially equal to a perimeter of said array of first regions;

a test unit coupled to said test structure and to said control test structure, for performing an electrical test on said test structure and said control test structure; and

an analyzer coupled to said test structure and to said control test structure, for determining a parameter as a function of said electrical test performed on said test structure and said control test structure.

14. The apparatus according to claim 13 , wherein:

said array of first regions comprise an array of shallow trench isolation regions;

said second region comprises a source/drain region;

said array of third regions comprise said array of shallow trench isolation regions; and

said fourth region comprises said source/drain region.

15. The apparatus according to claim 13 , wherein:

said array of first regions comprise an array of memory devices;

said second region comprises a field area;

said array of third regions comprise said array of memory devices; and

said fourth region comprises said field area.

16. The apparatus according to claim 15 , wherein said array of memory device comprises an array of flash memory devices.

17. The apparatus according to claim 13 , wherein:

said test structure further comprises a dielectric deposited upon said array of first regions and said second region; and

said control test structure further comprises a dielectric deposited upon said array of third regions and said fourth region.

18. The apparatus according to claim 17 , wherein said dielectric comprises a gate oxide layer.

19. The apparatus according to claim 17 , wherein said dielectric comprises a tunnel oxide layer.

20. The apparatus according to claim 17 , wherein:

said test structure further comprises a layer of polysilicon deposited upon said dielectric; and

said control test structure further comprises a layer of polysilicon deposed upon said dielectric.

21. The apparatus according to claim 13 , wherein said parameter is selected from a group consisting of silicon stress, crystal imperfection, crystalline dislocation, oxide layer imperfection.

22. The apparatus according to claim 13 , wherein said electrical test comprises a capacitance-voltage test.

23. The apparatus according to claim 13 , wherein said electrical test comprises a current injection test.

24. The apparatus according to claim 13 , further comprising a data storgae unit for storing said parameter.

Assignments (10)