Semiconductor memory and method of driving the same
View Patent ↗Immediately after data write, a negative voltage which has an absolute value lager than that in data erase and which falls within a range over which no FN current flows is applied to a control gate, and at the same time 0 V is applied to a silicon substrate, source, and drain. In this manner, electrons trapped in a first gate oxide film are detrapped into the silicon substrate. This prevents a memory cell from passing write verify although electrons stored in a nitride film are few, prevents data changes caused by a decrease in the read margin, and improves the data holding characteristic of a memory cell.
1. A semiconductor memory comprising:
a cell array including a plurality of memory cells each comprising:
an electron trapping layer formed above a semiconductor substrate, a control gate formed above said electron trapping layer;
a pair of a source and a drain formed in a surface region of said semiconductor substrate to sandwich a region below said control gate; and
a control circuit for performing control including:
a data erase operation for setting said control gate of a memory cell of said cell array at a negative voltage with respect to said semiconductor substrate; and
a detrap operation for making the absolute value of a negative voltage with respect to said semiconductor substrate, which is applied to said control gate, larger than that of the negative voltage during the data erase operation, and at the same time setting said source and drain at 0 V or at a positive voltage or floating said source and drain; wherein
the control circuit makes control such that the potential difference between the semiconductor substrate and the control gate upon a detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.
2. The memory according to claim 1 , wherein said electron trapping layer comprises a first gate insulating film formed on a semiconductor substrate, an electron trapping film formed on said first gate insulating film and made of an insulator, and a second gate insulating film formed on said electron trapping film.
3. The memory according to claim 2 , wherein in the detrap operation, said control circuit applies to said control gate a negative voltage within a range capable of preventing an FN current from flowing between said electron trapping layer and said semiconductor substrate.
4. The memory according to claim 2 , wherein said electron trapping layer is a nitride film.
5. The memory according to claim 1 , wherein in the detrap operation, said control circuit applies a negative voltage to said control gate and a positive voltage of the same magnitude to said semiconductor substrate, source, and drain, and
an electric field between said control gate and said semiconductor substrate, source, and drain applies a stress which is larger than that in the data erase operation.
6. The memory according to claim 1 , wherein said control circuit performs the detrap operation during a write sequence for writing data in said memory cell.
7. A semiconductor memory comprising:
a cell array including a plurality of memory cells each comprising:
an electron trapping layer formed above a semiconductor substrate,
a control gate formed above said electron trapping layer;
a pair of a source and a drain formed in a surface region of said semiconductor substrate to sandwich a region below said control gate; and
a control circuit for performing, during a sequence for writing data in a memory cell of said cell array, control including a detrap operation for setting said control gate at a negative voltage with respect to said semiconductor substrate, and at the same time setting said source and drain at 0 V or at a positive voltage or floating said source and drain; wherein
the control circuit makes control such that the potential difference between the semiconductor substrate and the control gate upon the detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.
8. The memory according to claim 7 , wherein said electron trapping layer comprises a first gate insulating film formed on a semiconductor substrate, an electron trapping film formed on said first gate insulating film and made of an insulator, and a second gate insulating film formed on said electron trapping film.
9. The memory according to claim 8 , wherein in the detrap operation, said control circuit applies to said control gate a negative voltage within a range capable of preventing an FN current from flowing between said electron trapping layer and said semiconductor substrate.
10. The memory according to claim 8 , wherein said electron trapping layer is a nitride film.
11. The memory according to claim 7 , wherein in the detrap operation, said control circuit applies a negative voltage to said control gate and a positive voltage of the same magnitude to said semiconductor substrate, source, and drain and an electric field between said control gate and said semiconductor substrate, source, and drain applies a stress which is larger than that in the data erase operation.
12. The memory according to claim 7 , wherein said control circuit performs the detrap operation immediately after writing data in said memory cell.
13. The memory according to claim 7 , wherein said control circuit performs the detrap operation at the end of a write sequence for writing data in said memory cell.
14. The memory according to claim 7 , wherein said control circuit performs the detrap operation when an operation performed in an erase sequence for erasing data in said memory cell is different from a data erase operation.
15. A semiconductor memory comprising:
a cell array including a plurality of memory cells each comprising:
an electron trapping layer formed above a semiconductor substrate,
a control gate formed above said electron trapping layer; and
a pair of a source and a drain formed in a surface region of said semiconductor substrate to sandwich a region below said control gate;
a control circuit for performing, when an operation performed in an erase sequence for erasing data in a memory cell of said cell array is different from the data erase operation, control including the detrap operation for setting said control gate at a negative voltage with respect to said semiconductor substrate, and at the same time setting said source and drain at 0 V or at a positive voltage or floating said source and drain; wherein
a control circuit makes control such that the potential difference between the semiconductor substrate and the control gate upon a detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon a data erase operation.
16. The memory according to claim 15 , wherein said electron trapping layer comprises a first gate insulating film formed on a semiconductor substrate, an electron trapping film formed on said first gate insulating film and made of an insulator, and a second gate insulating film formed on said electron trapping film.
17. The memory according to claim 16 , wherein in the detrap operation, said control circuit applies to said control gate a negative voltage within a range capable of preventing an FN current from flowing between said electron trapping layer and said semiconductor substrate.
18. The memory according to claim 16 , wherein said electron trapping layer is a nitride film.
19. The memory according to claim 15 , wherein in the detrap operation, said control circuit applies a negative voltage to said control gate and a positive voltage of the same magnitude to said semiconductor substrate, source, and drain, and
an electric field between said control gate and said semiconductor substrate, source, and drain applies a stress which is larger than that in the data erase operation.
20. The memory according to claim 15 , wherein said control circuit performs the detrap operation immediately after erasing data in said memory cell.
21. The memory according to claim 15 , wherein said control circuit performs the detrap operation at the end of an erase sequence for erasing data in said memory cell.
22. A method of driving a semiconductor memory which comprises a cell array including a plurality of memory cells each comprising:
an electron trapping layer formed above a semiconductor substrate,
a control gate formed above the electron trapping layer;
a pair of a source and a drain formed in a surface region of the semiconductor substrate to sandwich a region below the control gate,
comprising a control process for performing control including:
a data erase operation for setting the control gate of a memory cell of the cell array at a negative voltage with respect to the semiconductor substrate; and
a detrap operation for making the absolute value of a negative voltage with respect to the semiconductor substrate, which is applied to the control gate, larger than that of the negative voltage during the data erase operation, and at the same time setting the source and drain at 0 V or at a positive voltage or floating the source and drain; wherein
the control process makes control such that the potential difference between the semiconductor substrate and the control gate upon the detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.
23. The method according to claim 22 , wherein said electron trapping layer comprises a first gate insulating film formed on a semiconductor substrate, an electron trapping film formed on said first gate insulating film and made of an insulator, and a second gate insulating film formed on said electron trapping film.
24. The method according to claim 23 , wherein in the detrap operation, the control process applies to the control gate a negative voltage within a range capable of preventing an FN current from flowing between the electron trapping layer and the semiconductor substrate.
25. The method according to claim 22 , wherein the control process performs the detrap operation during a write sequence for writing data in the memory cell.
26. A method of driving a semiconductor memory which comprises a cell array including a plurality of memory cells each comprising:
an electron trapping layer formed above a semiconductor substrate,
a control gate formed above the election trapping layer;
a pair of a source and a drain formed in a surface region of the semiconductor substrate to sandwich a region below the control gate,
comprising a control process for performing, during a sequence for writing data in a memory cell of the cell array, control including a detrap operation for setting the control gate at a negative voltage with respect to the semiconductor substrate, and at the same time setting the source and drain at 0 V or at a positive voltage or floating the source and drain; wherein
the control process makes control such that the potential difference between the semiconductor substrate and the control gate upon the detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon the data erase operation.
27. The method according to claim 26 , wherein said electron trapping layer comprises a first gate insulating film formed on a semiconductor substrate, an electron trapping film formed on said first gate insulating film and made of an insulator, and a second gate insulating film formed on said electron trapping film.
28. The method according to claim 27 , wherein in the detrap operation, the control process applies to the control gate a negative voltage within a range capable of preventing an FN current from flowing between the electron trapping layer and the semiconductor substrate.
29. The method according to claim 26 , wherein the control process performs the detrap operation immediately after writing data in the memory cell.
30. The method according to claim 26 , wherein the control process performs the detrap operation at the end of a write sequence for writing data in the memory cell.
31. The memory according to claim 26 , wherein the control process performs the detrap operation when an operation performed in an erase sequence for erasing data in the memory cell is different from a data erase operation.
32. A method of driving a semiconductor memory which comprises a cell array including a plurality of memory cells each comprising:
an electron trapping layer formed above a semiconductor substrate,
a control gate formed above the electron trapping layer; and
a pair of a source and a drain formed in a surface region of the semiconductor substrate to sandwich a region below the control gate;
comprising a control process for performing, when an operation performed in an erase sequence for erasing data in the memory cell of the cell array is different from a data erase operation, control including a detrap operation for setting the control gate at a negative voltage with respect to the semiconductor substrate, and at the same time setting the source and drain at 0 V or at a positive voltage or floating the source and drain; wherein
the control process makes control such that the potential difference between the semiconductor substrate and the control gate upon a detrap operation is smaller than the potential difference between one of the source and drain in a pair and the control gate upon a data erase operation.
33. The method according to claim 32 , wherein said electron trapping layer comprises a first gate insulating film formed on a semiconductor substrate, an electron trapping film formed on said first gate insulating film and made of an insulator, and a second gate insulating film formed on said electron trapping film.
34. The method according to claim 33 , wherein in the detrap operation, the control process applies to the control gate a negative voltage within a range capable of preventing an FN current from flowing between the electron trapping layer and the semiconductor substrate.
35. The method according to claim 32 , wherein the control process performs the detrap operation immediately after erasing data in the memory cell.
36. The method according to claim 32 , wherein the control process performs the detrap operation at the end of an erase sequence for erasing data in the memory cell.