Apparatus for interfacing and testing a phase locked loop in a field programmable gate array
View Patent ↗An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.
1. An apparatus for interfacing a phase locked loop in a field programmable gate array, said apparatus comprising:
a phase locked loop cluster comprising:
a plurality of logic components designed to provide lock signals and clock signals,
a plurality of logic components that configure and provide control signals,
at least one driver module,
a plurality of receiver modules, and
at least one buffer module; and
a phase locked loop selectively coupled to an input/output pad and said phase locked loop cluster through a plurality of multiplexers.
2. The apparatus of claim 1 wherein said phase locked loop is selectively coupled to said input/output pad through said phase locked loop cluster and through a plurality of multiplexers.
3. The apparatus of claim 1 , wherein said phase locked loop cluster further comprises a feedback module that provides a feedback port signal to said phase locked loop.
4. The apparatus of claim 3 , wherein said phase locked loop comprises a first input and a second input, said first input receiving a reference clock signal from an input line through a delay line, and said second input is coupled to an output of a multiplexer through a delay line and a divider.
5. The apparatus of claim 4 , wherein said multiplexer receives said feedback port signal.
6. A method of interfacing a phase locked loop between a field programmable gate array core and at least one of a plurality of input/output pads comprising:
coupling a phase locked loop cell to the field programmable gate array core through a phase locked loop cluster, said phase locked loop cluster comprising a plurality of logic components designed to provide lock signals and clock signals, a plurality of logic components that configure and provide control signals, at least one driver module, a plurality of receiver modules, and at least one buffer module; and
coupling the at least one of a plurality of input/output pads to the phase locked loop cell,
wherein said phase locked loop cell is selectively coupled to said at least one of a plurality of input/output pads and said phase locked loop cluster through a plurality of multiplexers.
7. The method of claim 6 wherein the phase locked loop cluster is further coupled to the field programmable gate array core through an input/output cluster.
8. The method of claim 7 wherein the phase locked loop cluster is further coupled to the field programmable gate array core through at least one of a plurality of multiplexers.
9. The method of claim 6 , wherein said phase locked loop cluster further comprises a feedback module that provides a feedback port signal to said phase locked loop cell.
10. The method of claim 9 , wherein said phase locked loop cell comprises a first input and a second input, said first input receiving a reference clock signal from an input line through a delay line, and said second input is coupled to an output of a multiplexer through a delay line and a divider.
11. The method of claim 10 , wherein said multiplexer receives said feedback port signal.