Programmable multi-standard I/O architecture for FPGAS
View Patent ↗The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards.
1. A programmable input/output driver circuit comprising:
two or more P-channel pullup transistors;
two or more N-channel pulldown transistors;
each pullup or pulldown transistor is driven by a logic gate;
separate configuration signals driving each of above logic gates;
two or more input buffer types;
a multiplexer connected to said input buffers; and
configuration signals driving select input of said multiplexer.
2. The programmable input/output driver circuit of claim 1 where said configuration signals are generated by programmable antifuse matrix cells.
3. The programmable input/output driver circuit of claim 1 where said input buffer types are input standards.
4. The programmable input/output driver circuit of claim 1 where configuration signals can configure it to implement a plurality of I/O standards.
5. In a field programmable gate array (FPGA) having a logic array, a programmable input/output buffer architecture comprising:
at least one programmable input/output configuration means coupled to the FPGA logic array; and
a configurable input/output driver coupled to said programmable input/output configuration means and coupled to an input/output pad, said configurable input/output driver comprising two or more input buffer types and a multiplexer connected to said input buffers.
6. The programmable input/output buffer architecture according to claim 5 wherein said at least one programmable configuration means comprises a reprogrammable element.
7. The programmable input/output buffer architecture according to claim 5 wherein said at least one programmable configuration means comprises at least one EEPROM cell.
8. The programmable input/output buffer architecture according to claim 5 wherein said at least one programmable configuration means comprises at least one flash memory latch.
9. The programmable input/output buffer architecture according to claim 5 wherein said at least one programmable configuration means configures said configurable input/output driver to a plurality of input/output standards.
10. In a field programmable gate array (FPGA) having a logic array, a method of programming a programmable input/output buffer architecture comprising:
providing at least one programmable input/output buffer configuration means coupled to the FPGA logic array;
programming said at least one programmable input/output buffer configuration means to a desired configuration; and
configuring to said desired configuration a configurable input/output driver that is coupled to said programmable input/output configuration means and coupled to an input/output pad said configurable input/output driver comprising two or more input buffer types and a multiplexer connected to said input buffers.
11. The method of programming a programmable input/output buffer architecture according to claim 10 wherein said at least one programmable configuration means comprises a reprogrammable element.
12. The method of programming a programmable input/output buffer architecture according to claim 10 wherein said at least one programmable configuration means comprises at least one EEPROM cell.
13. The method of programming a programmable input/output buffer architecture according to claim 10 wherein said at least one programmable configuration means comprises at least one memory latch.
14. The method of programming a programmable input/output buffer architecture according to claim 10 wherein said at least one programmable configuration means configures said configurable input/output driver to a plurality of input/output standards.
15. A method for providing a programmable input/output driver circuit comprising:
providing two or more P-channel pullup transistors;
providing two or more N-channel pulldown transistors;
each pullup or pulldown transistor is driven by a logic gate;
providing separate configuration signals that drive each of the above logic gates;
providing two or more input buffer types;
providing a multiplexer connected to said input buffers, wherein said configuration signals drive select input of said multiplexer.
16. The method of claim 15 wherein said configuration signals are generated by programmable antifuse matrix cells.
17. The method of claim 15 wherein said input buffer types are input standards.
18. The method of claim 15 wherein said configuration signals can configure said programmable input/output driver circuit to implement a plurality of I/O standards.