CCD having improved flushing by reducing power consumption and creating a uniform dark field while maintaining low dark current
View Patent ↗A digital camera includes a CCD operating with accumulation mode clocking for capturing an electronic representation of an image; and two or more clocks operatively and respectively connected to each phase of the two or more phases for initiating flushing of excess current, wherein, to initiate flushing, a time the clocks are at a high level are substantially the same, and a time the clocks are at a low level can be selected at any duration between a minimum width at which dark current starts to substantially increase and twice its normal operating duration during image readout and for reducing power consumption while retaining minimum dark current and for having a substantially uniform dark field.
1. A digital camera comprising:
(a) a CCD having an array of pixels arranged in rows and columns with two or more phases per pixel and operating in accumulation mode clocking for capturing an electronic representation of an image; and
(b) means providing two or more clocks each being operatively and respectively connected to a phase of the pixels in a row for initiating flushing of excess current, and after flushing and capturing an image by the array of pixels reading out such pixels wherein, to initiate flushing, one clock is at its high level when the other clock is at its low level and as the high level is shifted to a low level, the low level is shifted to a high level and then after transfer of a row of excess charge both clocks are at a low level for a predetermined duration which is selected to be longer than the duration that either clock is at a high level to thereby reduce power levels, the predetermined duration being selected to be between a minimum duration at which dark current starts to substantially increase and a maximum of twice the duration of image readout of a row.
2. The digital camera as in claim 1 , wherein the time the clocks are high is substantially proportional to a square of a width of the CCD.
3. The digital camera as in claim 1 , wherein the CCD is a two-phase CCD.
4. An image sensor comprising:
(a) a CCD having an array of pixels arranged in rows and columns with two or more phases per pixel and operating in accumulation mode clocking for capturing an electronic representation of an image; and
(b) means providing two or more clocks each being operatively and respectively connected to a phase of the pixels in a row for initiating flushing of excess current, and after flushing and capturing an image by the array of pixels reading out such pixels wherein, to initiate flushing, one clock is at its high level when the other clock is at its low level and as the high level is shifted to a low level, the low level is shifted to a high level and then after transfer of a row of excess charge both clocks are at a low level for a predetermined duration which is selected to be longer than the duration that either clock is at a high level to thereby reduce power levels, the predetermined duration being selected to be between a minimum duration at which dark current starts to substantially increase and a maximum of twice the duration of image readout of a row.
5. The image sensor as in claim 4 , wherein the time the clocks are high is substantially proportional to a square of a width of the CCD.
6. The image sensor as in claim 4 , wherein the CCD is a two phase CCD.