Semiconductor device with high frequency parallel plate trench capacitor structure
View Patent ↗A semiconductor device ( 10 ) is formed on a semiconductor substrate ( 12 ) whose surface ( 24 ) is formed with a trench ( 18 ). A capacitor ( 20 ) has a first plate ( 22 ) formed over the substrate surface with first and second portions lining first and second sidewalls ( 25 ) of the trench, respectively. A second plate ( 35, 38 ) is formed over the first plate and extends into the trench between the first and second portions.
1. A semiconductor device, comprising:
a semiconductor substrate having a substrate surface formed with a plurality of adjacent trenches;
a capacitor formed in the plurality of adjacent trenches, the capacitor including a continuous first conductive layer formed over the substrate surface and lining sidewalls of the plurality of adjacent trenches to provide a first plate, a dielectric film formed over the first plate of the capacitor, and a second conductive material formed over the dielectric, wherein the second conductive material fills the plurality of adjacent trenches, and wherein the second conductive material in the plurality of adjacent trenches is directly coupled together to form a second plate of the capacitor; and
a trench substrate contact, wherein the continuous first conductive layer lines sidewalls of the trench substrate contact, and wherein the trench substrate contact is formed absent the second conductive material.
2. The semiconductor device of claim 1 , wherein the capacitor has a capacitance of at least one nanofarad.
3. The semiconductor device of claim 1 , wherein the dielectric film comprises silicon nitride.
4. The semiconductor device of claim 3 , wherein the dielectric film has a thickness in a range between about forty and about six hundred angstroms.
5. The semiconductor device of claim 1 , wherein the dielectric film extends over the first conductive layer above the substrate surface.
6. The semiconductor device of claim 1 , wherein the first plate is formed with polycrystalline silicon.
7. The semiconductor device of claim 6 , wherein the second plate is formed with polycrystalline silicon.
8. The semiconductor device of claim 7 , wherein the semiconductor substrate comprises a base layer of a first conductivity type.
9. The semiconductor device of claim 8 , wherein the first plate is doped to have the first conductivity type for providing an ohmic contact with the base layer.
10. The semiconductor device of claim 1 , further comprising a metallization layer formed over the substrate surface and electrically contacting the trench substrate contact.
11. The semiconductor device of claim 1 , wherein the first plate has a first thickness along the sidewalls and a second thickness substantially equal to the first thickness over the substrate surface.
12. The semiconductor device of claim 11 , wherein the substrate surface and a sidewall intersect at a corner and the first plate has a third thickness at the corner that is substantially equal to the first and second.
13. The semiconductor device of claim 1 , wherein a third conductive layer directly couples the second conductive material in the plurality of adjacent trenches together.
14. An integrated circuit, comprising:
a substrate having a substrate surface for defining a plurality of trenches;
a first conductive material disposed from the substrate surface along surfaces of the plurality of trenches, wherein the first conductive material is continuous between at least two trenches;
a second conductive material formed within the plurality of trenches and extending to the substrate surface;
a conductive layer directly coupling the second conductive material in adjacent trenches together; and
a dielectric formed within the plurality of trenches between the first and second conductive materials to provide a capacitance between the first and second conductive materials.
15. The integrated circuit of claim 14 , wherein a portion of the first conductive material is formed to overlie the substrate surface.
16. The integrated circuit of claim 15 , wherein a portion of the dielectric is formed over the portion of the first conductive material.
17. The integrated circuit of claim 16 , wherein a portion of the dielectric is formed over the substrate surface between the portions of the first and second conductive materials.
18. The integrated circuit of claim 14 , further comprising a trench substrate contact, wherein the first conductive material covers sidewalls and a bottom surface of the trench substrate contact, and wherein the trench substrate contact is formed absent the second conductive material.