IP Library Assignment 015328/0116
Patent Assignment
Reel/Frame 015328/0116

Security Interest

Recorded: 2004-05-21 Received: 2004-05-21 Pages: 16
Assignor
Assignee
JPMORGAN CHASE BANK, AS COLLATERAL AGENT
270 PARK AVENUE, NEW YORK, NY, 10017, UNITED STATES
Covered Properties (45)
Method of Forming a Self-Gated Transistor and Structure Therefor
Application: 10/813,501 →
Method of Forming a Floating Charge Pump and Structure Therefor
Application: 10/811,050 →
Low Audible Noise Power Supply Controller and Method Therefor
Application: 10/810,864 →
Method of Forming a Transistor Driver and Structure Therefor
Application: 10/805,405 →
High Voltage Lateral Fet Structure with Improved on Resistance Performance
Application: 10/797,537 →
Semiconductor Device Having Reduced Capacitance to Substrate and Method
Application: 10/773,853 →
Method of Forming an Eprom Cell and Structure Therefor
Application: 10/752,772 →
High Energy Esd Structure and Method
Application: 10/750,267 →
Semiconductor Device Having Reduced Gate Charge and Reduced on Resistance and Method
Application: 10/741,330 →
Method of Forming a Semiconductor Package and Leadframe Therefor
Application: 10/729,892 →
Lateral Fet Structure with Improved Blocking Voltage and on Resistance Performance and Method
Application: 10/729,292 →
Method of Forming a Leadframe for a Semiconductor Package
Application: 10/638,181 →
Method for Making a Direct Chip Attach Device and Structure
Application: 10/603,257 →
Power Management Method and Structure
Application: 10/374,099 →
Structure and Method of Forming a Multiple Leadframe Semiconductor Device
Application: 10/374,630 →
Method of Forming an Rf Detector and Structure Therefor
Application: 10/369,471 →
Power switching transistor with low drain to gate capacitance
Application: 10/369,236 →
Method of Forming a Variable Propagation Delay Semiconductor Device and Structure Therefor
Application: 10/369,230 →
Method of Forming a Bi-Directional Synchronization Controller
Application: 10/359,319 →
Power Switching Transistor with Low Drain to Gate Capacitance
Application: 10/313,225 →
Structure and Method of Making a High Performance Semiconductor Device Having a Narrow Doping Profile
Application: 10/307,590 →
Semiconductor Device with Parallel Plate Trench Capacitor and Method
Application: 10/305,773 →
Integrated Circuit with Vertical Pnp Transistor and Method
Application: 10/303,168 →
Integrated Inrush Current Limiter Circuit and Method
Application: 10/291,015 →
Integrated Inrush Current Limiter Circuit and Method
Application: 10/287,831 →
Semiconductor Device and Laminated Leadframe Package
Application: 10/270,401 →
Method of Forming a Low Resistance Semiconductor Device and Structure Therefor
Application: 10/270,419 →
Method of Forming an Audio Amplifier Voltage Reference and Structure Therefor
Application: 10/270,413 →
Structure and Method of Direct Chip Attach
Application: 10/237,123 →
Method of Forming a Power Device and Structure Therefor
Application: 10/228,374 →
Self-Aligned Vertical Gate Semiconductor Device
Application: 10/219,190 →
Method of Making a Vertical Gate Semiconductor Device
Application: 10/219,167 →
Circuit and Method for a Programmable Reference Voltage
Application: 10/217,497 →
Programmable Data Device and Method Therefor
Application: 10/217,661 →
Integrated Circuit and Laminated Leadframe Package
Application: 10/215,279 →
Method of Forming a Semiconductor Device and Structure Therefor
Application: 10/189,748 →
Integrated Circuit and Laminated Leadframe Package
Application: 10/183,287 →
Low Cost Method of Providing a Semiconductor Device Having a High Channel Density
Application: 10/184,187 →
Semiconductor Filter Circuit and Method
Application: 10/166,288 →
Method of Forming a Voltage Regulator Semiconductor Device Having Feedback and Structure Therefor
Application: 10/156,285 →
Voltage Mode Voltage Regulator with Current Mode Start-Up
Application: 10/153,986 →
Power Amplifier Driver and Method of Using
Application: 10/138,973 →
Thermal Shutdown Circuit with Hysteresis and Method of Using
Application: 10/133,761 →
Structure and Method of Forming a Multiple Leadframe Semiconductor Device
Application: 10/133,527 →
Smart Card Reader Circuit and Method of Monitoring
Application: 09/845,114 →