Semiconductor device having reduced gate charge and reduced on resistance and method
View Patent ↗In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.
1. A method of fabricating a semiconductor device comprising the steps of:
providing a semiconductor material having a first conductivity type and a first major surface;
forming first and second body regions of a second conductivity type in the semiconductor material, wherein the first and second body regions are separated by a JFET region of the first conductivity type;
forming a first source region of the first conductivity type in the first body region; and
forming a gate layer comprising a conductive material overlying the first major surface of the semiconductor material having a first opening over the JFET region and a second opening over the first body region, wherein the first opening is configured for reducing gate to drain capacitance.
2. The method of claim 1 further comprising the step of forming a first doped region of the first conductivity type in the JFET region, wherein the first doped region has a higher doping concentration than the semiconductor material.
3. The method of claim 1 further comprising the step of forming an interlevel dielectric layer overlying the first major surface and within the first opening.
4. The method of claim 1 wherein the step of forming the first and second body regions comprises using an angled implant of approximately 20 to 60 degrees.
5. The method of claim 1 wherein the step of forming the first and second body regions comprises using an angled implant of approximately 35 to 60 degrees.
6. The method of claim 1 wherein the step of forming the first and second body regions comprises implanting boron with a dose in the range of 1.5×10 13 to 6×10 13 atoms/cm 2 .
7. The method of claim 1 further comprising the steps of:
forming a spacer within the second opening in the gate layer;
forming a second doped region of the second conductivity type in the first body region;
forming and patterning a first metal layer over the semiconductor material to form a gate metal layer electrically coupled to the gate layer and a source metal layer electrically coupled to the first source region; and
forming a second metal layer on a second major surface of the semiconductor material.
8. The method of claim 1 wherein forming the first opening comprises forming the first opening over substantially all of the JFET region.
9. The method of claim 1 wherein forming the first opening comprises forming the first opening over about 30% to 100% percent of the JFET region.
10. The method of claim 1 wherein the semiconductor device is comprised of a vertical power MOSFET.
11. A method of fabricating a vertical semiconductor device comprising the steps of:
providing a semiconductor material having a first conductivity type and a first major surface;
forming a first and second body regions of a second conductivity type opposite the first conductivity type in the semiconductor material extending from the first major surface of the semiconductor material into a portion of semiconductor material, wherein a JFET region of the first conductivity type separates the first body region from the second body region;
forming a source region of first conductivity type in the first body region;
forming a gate dielectric layer overlying the JFET region and at least portions of the first and second body regions;
forming a gate layer comprising a conductive material overlying the gate dielectric layer;
forming a first dielectric layer over the gate layer;
forming a first opening in the first dielectric layer and the gate layer over the JFET region;
forming a second opening in the first dielectric layer and the gate layer over the first body region, wherein the first opening and the second opening are formed during the same step; and
configuring a second dielectric layer within the first opening to reduce gate to drain capacitance when the semiconductor device is in operation.
12. A method for forming a vertical MOSFET device comprising the steps of:
providing a semiconductor material having a first conductivity type and a first major surface;
forming first and second body regions of a second conductivity type opposite the first conductivity type in the semiconductor material extending from the first major surface of the semiconductor material into a portion of semiconductor material, wherein the first and second body regions are spaced apart with a JFET region of the first conductivity type there between;
forming a first source region of the first conductivity type in the first body region;
forming a second source region of the first conductivity type in the second body region;
forming a conductive gate layer overlying the first major surface of the semiconductor material having a first opening over the JFET region configured to reduce gate charge, a second opening over the first body region, and a third opening over the second body region; and
forming a dielectric layer within the first opening.
13. The method of claim 12 further comprising the step of forming a doped region of the first conductivity type in JFET region through the first opening, wherein the doped region has a higher doping concentration than the semiconductor material and is configured to reduce on-resistance.
14. The method of claim 12 , wherein the step of forming the first and second body regions includes forming the first and second body regions comprising a single body design.
15. The method of claim 12 , wherein the step of forming the first and second body regions includes forming the first and second body regions, wherein the first and second body regions comprise a cellular design.