Method of forming a transistor driver and structure therefor
View Patent ↗In one embodiment, a power supply system has a transistor driver that receives a PWM signal and generates signals to drive output transistors of the power supply system in response to the PWM signal. If the PWM signal is low for a certain length of time, the transistor driver disables t least one of the output transistors.
1. A method of forming a synchronous rectifier driver comprising:
coupling a disable circuit to receive a PWM signal and to responsively provide a disable signal when the PWM signal remains at a first state for at least a first time period;
coupling a first control channel to receive the disable signal and responsive generate a first drive signal suitable for disabling a lower output transistor; and
coupling the first control channel to receive the PWM signal and responsively generate the first drive signal suitable for enabling the lower output transistor when the PWM signal is at the first state for less than the first time period.
2. The method of claim 1 further including coupling a second control channel to receive the PWM signal and responsively provide a second enable signal suitable for enabling an upper output transistor when the PWM signal is at a second state.
3. The method of claim 1 further including coupling a second control channel to receive the disable signal and responsively generate a second drive signal suitable for disabling an upper output transistor.
4. A method of forming a synchronous rectifier driver comprising;
coupling a disable circuit to receive a PWM signal and to responsively provide a disable signal when the PWM signal remains at a first state for at least a first time period and coupling the disable circuit to start a timer to generate the first time period when the PWM signal transitions from the first state to a second state; and
coupling a first control channel to receive the disable signal and responsive generate a first drive signal suitable for disabling a lower output transistor.
5. The method of claim 4 wherein coupling the disable circuit to start the timer to generate the first time period includes coupling the disable circuit to receive the PWM signal and responsively couple a current source to charge a capacitor.
6. The method of claim 5 further including coupling the disable circuit to receive the transition from the second state to the first state and responsively couple the capacitor to a discharge voltage.
7. The method of claim 5 further including coupling the capacitor to a comparator.
8. A synchronous rectifier driver comprising:
a disable circuit operable to receive a PWM signal and responsively generate a disable signal when the PWM signal remains in a first state for at least a first time period;
an upper transistor control channel operable to provide a first drive signal suitable to enable a first output transistor when the PWM signal is at a second state; and
a lower transistor control channel operable to provide a second drive signal suitable to enable a second output transistor when the PWM signal is at the first state for no greater than the first time period and operable to receive the disable signal and responsively provide a third drive signal suitable to disable the second output transistor.
9. The synchronous rectifier driver of claim 8 further including the upper transistor control channel operable to receive the disable signal and responsively disable the first output transistor.
10. The synchronous rectifier driver of claim 8 wherein the disable circuit operable to receive the PWM signal and responsively generate the disable signal when the PWM signal remains in a first state for at least the first time period includes the disable circuit operable to force the first drive signal and the second drive signal to a state suitable for disabling the first output transistor and the second output transistor.
11. The synchronous rectifier driver of claim 8 wherein the disable circuit includes a timer that generates the first time period wherein the timer is reset each time the PWM signal transitions from the first state to the second state.
12. A method of operating a power supply controller comprising:
generating a PWM signal;
enabling a first output transistor when the PWM signal is in a first state;
enabling a second output transistor when the PWM signal is in a second state for less than a first time period; and
disabling the second output transistor when the PWM signal is in the second state for at least the first time period.
13. The method of claim 12 wherein enabling the first output transistor when the PWM signal is in the first state includes enabling the first output transistor to supply current to an inductor.
14. The method of claim 13 wherein enabling the second output transistor when the PWM signal is in the second state includes enabling the second output transistor to sink current from the inductor.
15. The method of claim 12 further including disabling the first output transistor when the PWM signal is in the second state for at least the first time period.