Multi-level routing architecture in a field programmable gate array having transmitters and receivers
View Patent ↗A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.
1. A field programmable gate array (FPGA) comprising:
a plurality of logic clusters arranged in rows and columns, each logic cluster comprising a plurality of receiver modules, a plurality of transmitter modules, at least one buffer module, at least one sequential logic component, and a first combinatorial logic component;
a first-level routing architecture programmably coupled to said plurality of logic clusters;
a second-level routing architecture programmably coupled to said first-level routing architecture through at least one of said plurality of transmitter modules and at least one of said plurality of receiver modules; and
wherein at least one of said plurality of receiver modules comprises a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture, and at least one of said plurality of receiver modules can receive signals from said second-level routing architecture to said first-level routing architecture.
2. The FPGA of claim 1 wherein at least one of said plurality of transmitter modules comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and one of said inputs is coupled to said second-level routing architecture;
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture; and
wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routing architecture and can transmit signals from a vertical channel of said second-level routing architecture to a plurality of horizontal channels of said second-level routing architecture.
3. A routing architecture in a field programmable gate array (FPGA) comprising:
a plurality of input/output (I/O) clusters, said I/O clusters comprising a plurality of receiver modules, a plurality of transmitter modules, at least one buffer module, and an I/O component;
a first-level routing architecture programmably coupled to at least one of said plurality of I/O clusters; and
a second-level routing architecture programmably coupled to at least one of said plurality of I/O clusters and to said first-level routing architecture through at least one of said plurality of transmitter modules and at least one of said plurality of receiver modules.
4. The FPGA of claim 3 wherein at least one of said plurality of transmitter modules further comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and one of said inputs is coupled to said second-level routing architecture;
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture; and
wherein at least one of said plurality of transmitter modules can transmit all signals from said first-level routing architecture to said second-level routing architecture and transfer signals from all second-level vertical channels to two second-level horizontal channels.
5. The FPGA of claim 3 wherein at least one of said plurality of receiver modules further comprises:
a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture; and
wherein at least one of said plurality of receiver modules can receive all signals from said second-level horizontal and vertical routing architecture to said first-level routing architecture.
6. A method of forming a routing architecture in a field programmable gate array (FPGA) comprising:
providing a plurality of logic clusters arranged in rows and columns, each logic cluster comprising a plurality of receiver modules, a plurality of transmitter modules, at least one buffer module, at least one sequential logic component, and a first combinatorial logic component;
programmably coupling a first-level routing architecture to said logic clusters;
programmably coupling a second-level routing architecture to said first-level routing architecture through at least one of said plurality of transmitter modules and at least one of said plurality of receiver modules; and
wherein at least one of said plurality of receiver modules comprises a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture, and at least one of said plurality of receiver modules can receive signals from a vertical channel and a horizontal channel in said second-level routing architecture and can transmit said signals to said first-level routing architecture.
7. The method of claim 6 wherein at least one of said plurality of transmitter modules comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and at least one of said inputs is coupled to said second-level routing architecture;
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture; and
wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routing architecture and can transmit signals from vertical channels to a plurality of horizontal channels of said second-level routing architecture.
8. A method of forming a routing architecture in a field programmable gate array (FPGA) comprising:
providing a plurality of input/output (I/O) clusters, said I/O clusters comprising a plurality of receiver modules, a plurality of transmitter modules, at least one buffer module, and an I/O component;
programmably coupling a first-level routing architecture to at least one of said plurality of I/O clusters; and
programmably coupling a second-level routing architecture to at least one of said plurality of I/O clusters and to said first-level routing architecture through at least one of said plurality of transmitter modules and at least one of plurality of receiver modules.
9. The method of claim 8 wherein at least one of said plurality of transmitter modules further comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and at least one of said inputs is coupled to said second-level routing architecture;
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture; and
wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routing architecture and can transmit signals between a vertical channel of said second-level routing architecture to a plurality of horizontal channels of second-level routing architecture.
10. The method of claim 8 wherein at least one of said plurality of receiver modules further comprises:
a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture; and
wherein at least one of said plurality of receiver modules can receive signals from a vertical channel in said second-level routing architecture and a horizontal channel in said second-level routing architecture and can transmit said signals to said first-level routing architecture.
11. In a field programmable gate array (FPGA) comprising a plurality of logic clusters arranged in rows and columns, each of said plurality of logic clusters comprising:
a plurality of receiver modules, a plurality of transmitter modules, at least one buffer module, at least one sequential logic component, and a first combinatorial logic component, and a method of routing a signal between a first-level routing architecture and a second-level routing architecture comprising:
programming a first programmable element to couple at least one of a plurality of routing tracks in said first-level routing architecture to at least one of said plurality of transmitter modules of said logic cluster;
programming a second programmable element to couple at least one of said plurality of transmitter modules to at least one of a plurality of tracks of said second-level routing architecture; and
sending the signal from said at least one of a plurality of tracks of the first-level routing architecture to at least one of a plurality of tracks of the second-level routing architecture.
12. The method of claim 11 , wherein said programming said first programmable element and said programming said second programmable element comprises programming at least one antifuse.
13. A field programmable gate array (FPGA) comprising:
a plurality of logic clusters arranged in rows and columns, each logic cluster comprising a plurality of receiver modules, a plurality of transmitter modules, at least one buffer module, at least one sequential logic component, and a first combinatorial logic component;
a first-level routing architecture programmably coupled to said plurality of logic clusters;
a second-level routing architecture programmably coupled to said first-level routing architecture through at least one of said plurality of transmitter modules and at least one of said plurality of receiver modules; and
wherein at least one of said plurality of transmitter modules comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and one of said inputs is coupled to said second-level routing architecture;
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture; and
wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routing architecture and can transmit signals from a vertical channel of said second-level routing architecture to a plurality of horizontal channels of said second-level routing architecture.
14. The FPGA of claim 13 , wherein at least one of said plurality of receiver modules comprises:
a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture; and
wherein at least one of said plurality of receiver modules can receive signals from said second-level routing architecture to said first-level routing architecture.
15. A method of forming a routing architecture in a field programmable gate array (FPGA) comprising:
providing a plurality of logic clusters arranged in rows and columns, each logic cluster comprising a plurality of receiver modules, a plurality of transmitter modules, at least one buffer module, at least one sequential logic component, and a first combinatorial logic component;
programmably coupling a first-level routing architecture to said logic clusters;
programmably coupling a second-level routing architecture to said first-level routing architecture through at least one of said plurality of transmitter modules and at least one of said plurality of receiver modules; and
wherein at least one of said plurality of transmitter modules comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and at least one of said inputs is coupled to said second-level routing architecture;
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture; and
wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routing architecture and can transmit signals from vertical channels to a plurality of horizontal channels of said second-level routing architecture.
16. The method of claim 15 , wherein at least one of said plurality of receiver modules comprises:
a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture; and
wherein at least one of said plurality of receiver modules can receive signals from a vertical channel and a horizontal channel in said second-level routing architecture and can transmit said signals to said first-level routing architecture.