IP Library Granted Patent US 6,972,967
Granted Patent B2
US 6,972,967 · App. 10/372,058 · Granted Dec 6, 2005

EMC/ESD mitigation module

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Quick Facts
Patent No.
US 6,972,967
App. No.
10/372,058
Granted
Dec 6, 2005
Kind
B2
Abstract

An assembly for mitigating at least one of an electrostatic discharge and electromagnetic interference is provided. The assembly includes (a) first and second spaced apart electrical conductors 108 and 116 and (b) a mitigation module 300 electrically coupled to the first and second spaced apart electrical conductors to control a magnitude of an electrostatic discharge and/or electromagnetic interference in the first and second electrical conductors 108 and 116 . One or more of the following statements is true: (i) the mitigation module 300 comprises a ferrite material 304 ; (ii) the mitigation module 300 comprises a lossy dielectric material 308 ; and (iii) an equivalent electrical circuit for at least part of the mitigation module 300 comprises at least a first circuit segment 512 comprising a first inductor and a first capacitor electrically connected in parallel and a second capacitor 504 electrically connected in series with the first circuit segment 512 . The first and second electrical conductors can be, for example, a ground plane of a printed circuit board 108 and a wall of the enclosure or chassis 116.

Claims (65)

1. A module for mitigating at least one of an electrostatic discharge and electromagnetic interference, comprising:

an outer electrically conductive sidewall comprising a conductive material;

a ferrite material spaced apart from and located interiorly of the sidewall; and

a dielectric material located between the sidewall and the ferrite material, wherein first and second capacitances are defined, respectively, between first and second portions of the ferrite material and first and second spaced apart portions of the conductive material, the first portion of the ferrite material being spaced from the first portion of the conductive material and the second portion of the ferrite material being spaced from the second portion of the conductive material and a third capacitance is defined between the first and second spaced apart portions of the ferrite material and wherein each of the first and second capacitances is greater than the third capacitance.

2. The module of claim 1 , wherein an equivalent electrical circuit for at least part of the mitigation module comprises at least a first circuit segment comprising at least a first inductor and a first capacitor electrically connected in parallel and at least a second capacitor electrically connected in series with the first circuit segment.

3. The module of claim 1 , wherein the module is electrically coupled to at least one of a ground plane of a printed circuit board and at least part of an enclosure surrounding the printed circuit board.

4. The module of claim 1 , the ferrite material is at least one of a manganese-based and zinc-based.

5. The module of claim 3 , wherein the ferrite material is located between and spaced apart from each of the ground plane and the at least part of the enclosure.

6. The module of claim 1 , wherein the dielectric material is a lossy dielectric material.

7. The module of claim 6 , wherein the lossy dielectric material is at least one of a ceramic material and glass.

8. The module of claim 2 , wherein the first circuit segment is defined by the ferrite material.

9. The module of claim 2 , wherein the second capacitor is defined by the outer conductive wall, the ferrite material, and a dielectric material positioned between the outer conductive wall and the ferrite material.

10. The module of claim 1 , wherein the module comprises first and second stacked sections, with each stacked section comprising a portion of the ferrite material, a portion of the dielectric material, and a portion of the outer conductive wall.

11. The module of claim 10 , wherein the first portion of the ferrite material in the first section is spaced apart from the second portion of the ferrite material in the second section.

12. The module of claim 11 , wherein the first and second sections are separated by a conductive spacer ring.

13. The module of claim 1 , wherein the outer conductive wall comprises a sidewall and endwalls and wherein the ferrite material is spaced apart from the sidewall and the end walls.

14. The module of claim 13 , wherein the module comprises first and second spaced apart sidewall sections comprising respectively the first and second portions of the conductive material and an insulative spacer ring located between the first and second spaced apart sidewall sections.

15. The module of claim 1 , wherein the module is positioned between and in contact with the first and second electrical conductors and comprises first and second insulative annular spacer rings, wherein the ferrite passes through the annuli of the first and second insulative spacer rings and is in electrical contact with the first and second electrical conductors, and wherein the first and second insulative annular spacer rings separate the dielectric material and the outer conductive wall from the first and second electrical conductors.

16. The module of claim 12 , wherein the module is positioned between and in contact with the first and second electrical conductors.

17. In an assembly comprising at least first and second spaced apart electrical conductors and a mitigation module electrically coupled to at least one of the first and second spaced apart electrical conductors to mitigate a magnitude of at least one of an electrostatic discharge and electromagnetic interference in at least one of the first and second electrical conductors, the mitigation module including a ferrite material, a lossy dielectric material, and a conductive material, a method comprising:

when the at least one of an electrostatic discharge and electromagnetic interference is passed through the mitigation module, the following substeps are performed:

(a) passing the at least one of an electrostatic discharge and electromagnetic interference through the conductive material;

(b) thereafter passing the at least one of an electrostatic discharge and electromagnetic interference through the lossy dielectric material; and

(c) thereafter passing the at least one of an electrostatic discharge and electromagnetic interference through the ferrite material.

18. The method of claim 17 , wherein the first electrical conductor is a ground plane of a printed circuit board and the second electrical conductor is at least part of an enclosure surrounding the printed circuit board and wherein an equivalent electrical circuit for at least part of the mitigation module comprises at least a first circuit segment comprising at least a first inductor and a first capacitor electrically connected in parallel and at least a second capacitor electrically connected in series with the first circuit segment.

19. The method of claim 17 , further comprising before substep (a):

passing the at least one of an electrostatic discharge and electromagnetic interference through the ferrite material;

thereafter passing the at least one of an electrostatic discharge and electromagnetic interference through the lossy dielectric material.

20. The method of claim 17 , the ferrite material is at least one of a manganese-based and zinc-based.

21. The method of claim 17 , wherein in the module the ferrite material is spaced apart from an outer conductive wall of the module.

22. The method of claim 21 , wherein the ferrite material is spaced apart from each of the first and second electrical conductors.

23. The method of claim 17 , further comprising after substep (c):

(d) passing the at least one of an electrostatic discharge and electromagnetic interference through the lossy dielectric material;

(e) thereafter passing the at least one of an electrostatic discharge and electromagnetic interference through the conductive material.

24. The method of claim 17 , wherein the lossy dielectric material is at least one of a ceramic material and glass.

25. The method of claim 17 , wherein first and second capacitances are defined, respectively, between first and second portions of the ferrite material and first and second spaced apart portions of the conductive material, the first portion of the ferrite material being spaced from the first portion of the conductive material and the second portion of the ferrite material being spaced from the second portion of the conductive material and a third capacitance is defined between the first and second spaced apart portions of the ferrite material and wherein each of the first and second capacitances is greater than the third capacitance.

26. The method of claim 18 , wherein the first circuit segment is defined by the ferrite material.

27. The method of claim 26 , wherein the second capacitor is defined by an outer conductive wall of the module spaced apart from the ferrite material and the dielectric material positioned between the outer conductive wall and the ferrite material and wherein the outer conductive wall comprises the conductive material.

28. The method of claim 27 , wherein the module comprises first and second stacked sections, with each stacked section comprising a portion of the ferrite material, a portion of the dielectric material, and a portion of the outer conductive wall.

29. The method of claim 28 , wherein the portion of the ferrite material in the first section is spaced apart from the portion of the ferrite material in the second section.

30. The method of claim 29 , wherein the first and second sections are separated by a conductive spacer ring.

31. The method of claim 30 , wherein the outer conductive wall comprises a sidewall and endwalls and wherein the ferrite material is spaced apart from the sidewall and the end walls.

32. The method of claim 31 , wherein the module comprises first and second spaced apart sidewall sections and an insulative spacer ring located between the first and second spaced apart sidewall sections.

33. The method of claim 27 , wherein the module is positioned between and in contact with the first and second electrical conductors and comprises first and second insulative annular spacer rings, wherein the ferrite passes through the annuli of the first and second insulative spacer rings and is in electrical contact with the first and second electrical conductors, and wherein the first and second insulative annular spacer rings separate the dielectric material and the outer conductive wall from the first and second electrical conductors.

34. The method of claim 32 , wherein the module is positioned between and in contact with the first and second electrical conductors.

35. An assembly for mitigating at least one of an electrostatic discharge and electromagnetic interference, comprising:

at least first and second spaced apart electrical conductors; and

a mitigation module electrically coupled to at least one of the first and second spaced apart electrical conductors to control a magnitude of at least one of an electrostatic discharge and electromagnetic interference in at least one of the first and second electrical conductors, wherein the mitigation module comprises a ferrite material; and a lossy dielectric material and wherein a conductive material and first and second capacitances are defined, respectively, between first and second portions of the ferrite material and first and second spaced apart portions of the conductive material, the first portion of the ferrite material being spaced from the first portion of the conductive material and the second portion of the ferrite material being spaced from the second portion of the conductive material and a third capacitance is defined between the first and second spaced apart portions of the ferrite material and wherein each of the first and second capacitances is greater than the third capacitance.

36. The assembly of claim 35 , wherein the first electrical conductor is a ground plane of a printed circuit board and the second electrical conductor is at least part of an enclosure surrounding the printed circuit board.

37. The assembly of claim 35 , wherein an equivalent electrical circuit for at least part of the mitigation module comprises at least a first circuit segment comprising at least a first inductor and a first capacitor electrically connected in parallel and at least a second capacitor electrically connected in series with the first circuit segment.

38. The assembly of claim 37 , the ferrite material is at least one of a manganese-based and zinc-based.

39. The assembly of claim 37 , wherein in the module the ferrite material is spaced apart from an outer conductive wall of the module.

40. The assembly of claim 39 , wherein the ferrite material is spaced apart from each of the first and second electrical conductors.

41. The assembly of claim 35 , wherein the first and second capacitances are approximately equivalent.

42. The assembly of claim 35 , wherein the lossy dielectric material is at least one of a ceramic material and glass.

43. The assembly of claim 35 , wherein the lossy dielectric material is positioned between the first and second portions of the ferrite material and the first and second portions of the conductive material.

44. The assembly of claim 37 , wherein the first circuit segment is defined by a ferrite material.

45. The assembly of claim 44 , wherein the second capacitor is defined by an outer conductive wall of the module spaced apart from the ferrite material and a dielectric material positioned between the outer conductive wall and the ferrite material.

46. The assembly of claim 45 , wherein the module comprises first and second stacked sections, with each stacked section comprising a portion of the ferrite material, a portion of the dielectric material, and a portion of the outer conductive wall.

47. The assembly of claim 46 , wherein the portion of the ferrite material in the first section is spaced apart from the portion of the ferrite material in the second section.

48. The assembly of claim 47 , wherein the first and second sections are separated by a conductive spacer ring.

49. The assembly of claim 46 , wherein the outer conductive wall comprises a sidewall and endwalls and wherein the ferrite material is spaced apart from the sidewall and the end walls.

50. The assembly of claim 49 , wherein the module comprises first and second spaced apart sidewall sections and an insulative spacer ring located between the first and second spaced apart sidewall sections.

51. The assembly of claim 45 , wherein the module is positioned between and in contact with the first and second electrical conductors and comprises first and second insulative annular spacer rings, wherein the ferrite passes through the annuli of the first and second insulative spacer rings and is in electrical contact with the first and second electrical conductors, and wherein the first and second insulative annular spacer rings separate the dielectric material and the outer conductive wall from the first and second electrical conductors.

52. The assembly of claim 35 , wherein the module is positioned between and in contact with the first and second electrical conductors.

Assignments (24)
(SECURITY INTEREST) GRANTOR'S NAME CHANGE Recorded Sep 21, 2023
From: AVAYA INC.
To: AVAYA LLC
Reel/Frame 065019/0231 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 53955/0436) Recorded May 18, 2023
From: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: AVAYA MANAGEMENT L.P.; AVAYA INC.; INTELLISIST, INC.; AVAYA INTEGRATED CABINET SOLUTIONS LLC
Reel/Frame 063705/0023 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 61087/0386) Recorded May 18, 2023
From: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: AVAYA MANAGEMENT L.P.; AVAYA INC.; INTELLISIST, INC.; AVAYA INTEGRATED CABINET SOLUTIONS LLC
Reel/Frame 063690/0359 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 045034/0001) Recorded May 18, 2023
From: GOLDMAN SACHS BANK USA., AS COLLATERAL AGENT
To: AVAYA INC.; INTELLISIST, INC.; AVAYA INTEGRATED CABINET SOLUTIONS LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES, INC.; ZANG, INC. (FORMER NAME OF AVAYA CLOUD INC.); HYPERQUALITY, INC.; HYPERQUALITY II, LLC; CAAS TECHNOLOGIES, LLC; AVAYA MANAGEMENT L.P.
Reel/Frame 063779/0622 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded May 4, 2023
From: AVAYA INC.; AVAYA MANAGEMENT L.P.; INTELLISIST, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 063542/0662 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded May 3, 2023
From: AVAYA MANAGEMENT L.P.; AVAYA INC.; INTELLISIST, INC.; KNOAHSOFT INC.
To: WILMINGTON SAVINGS FUND SOCIETY, FSB [COLLATERAL AGENT]
Reel/Frame 063742/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 45124/FRAME 0026 Recorded Apr 26, 2023
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: AVAYA HOLDINGS CORP.; AVAYA INC.; AVAYA MANAGEMENT L.P.; AVAYA INTEGRATED CABINET SOLUTIONS LLC
Reel/Frame 063457/0001 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Aug 5, 2022
From: AVAYA INC.; INTELLISIST, INC.; AVAYA MANAGEMENT L.P.; AVAYA CABINET SOLUTIONS LLC
To: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 061087/0386 →
BANKRUPTCY COURT ORDER RELEASING THE SECURITY INTEREST RECORDED AT REEL/FRAME 020156/0149 Recorded Jul 25, 2022
From: CITIBANK, N.A., AS ADMINISTRATIVE AGENT
To: AVAYA, INC.; AVAYA TECHNOLOGY LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES
Reel/Frame 060953/0412 →
SECURITY INTEREST Recorded Sep 25, 2020
From: AVAYA INC.; AVAYA MANAGEMENT L.P.; INTELLISIST, INC.; AVAYA INTEGRATED CABINET SOLUTIONS LLC
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 053955/0436 →
SECURITY INTEREST Recorded Jan 23, 2018
From: AVAYA INC.; AVAYA INTEGRATED CABINET SOLUTIONS LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES, INC.; ZANG, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 045124/0026 →
SECURITY INTEREST Recorded Jan 10, 2018
From: AVAYA INC.; AVAYA INTEGRATED CABINET SOLUTIONS LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES, INC.; ZANG, INC.
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 045034/0001 →
RELEASE OF SECURITY INTEREST Recorded Jan 9, 2018
From: CITICORP USA, INC.
To: AVAYA, INC.; SIERRA HOLDINGS CORP.; AVAYA TECHNOLOGY, LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES, INC.
Reel/Frame 045032/0213 →
BANKRUPTCY COURT ORDER RELEASING ALL LIENS INCLUDING THE SECURITY INTEREST RECORDED AT REEL/FRAME 041576/0001 Recorded Dec 15, 2017
From: CITIBANK, N.A.
To: AVAYA INC.; AVAYA INTEGRATED CABINET SOLUTIONS INC.; OCTEL COMMUNICATIONS LLC (FORMERLY KNOWN AS OCTEL COMMUNICATIONS CORPORATION); VPNET TECHNOLOGIES, INC.
Reel/Frame 044893/0531 →
BANKRUPTCY COURT ORDER RELEASING ALL LIENS INCLUDING THE SECURITY INTEREST RECORDED AT REEL/FRAME 025863/0535 Recorded Dec 15, 2017
From: THE BANK OF NEW YORK MELLON TRUST, NA
To: AVAYA INC.
Reel/Frame 044892/0001 →
BANKRUPTCY COURT ORDER RELEASING ALL LIENS INCLUDING THE SECURITY INTEREST RECORDED AT REEL/FRAME 030083/0639 Recorded Dec 15, 2017
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: AVAYA INC.
Reel/Frame 045012/0666 →
SECURITY INTEREST Recorded Jan 27, 2017
From: AVAYA INC.; AVAYA INTEGRATED CABINET SOLUTIONS INC.; OCTEL COMMUNICATIONS CORPORATION; VPNET TECHNOLOGIES, INC.
To: CITIBANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041576/0001 →
SECURITY AGREEMENT Recorded Mar 13, 2013
From: AVAYA, INC.
To: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., THE
Reel/Frame 030083/0639 →
SECURITY AGREEMENT Recorded Feb 22, 2011
From: AVAYA INC., A DELAWARE CORPORATION
To: BANK OF NEW YORK MELLON TRUST, NA, AS NOTES COLLATERAL AGENT, THE
Reel/Frame 025863/0535 →
CONVERSION FROM CORP TO LLC Recorded Dec 29, 2008
From: AVAYA TECHNOLOGY CORP.
To: AVAYA TECHNOLOGY LLC
Reel/Frame 022071/0420 →
REASSIGNMENT Recorded Jun 27, 2008
From: AVAYA TECHNOLOGY LLC
To: AVAYA INC
Reel/Frame 021158/0319 →
SECURITY AGREEMENT Recorded Nov 28, 2007
From: AVAYA, INC.; AVAYA TECHNOLOGY LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES, INC.
To: CITICORP USA, INC., AS ADMINISTRATIVE AGENT
Reel/Frame 020166/0705 →
SECURITY AGREEMENT Recorded Nov 27, 2007
From: AVAYA, INC.; AVAYA TECHNOLOGY LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES, INC.
To: CITIBANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 020156/0149 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2003
From: NORTE, DAVID A.; YOON, WOONG K.; TRAN, THU-DUYEN NGOC
To: AVAYA TECHNOLOGY CORP.
Reel/Frame 013814/0402 →