Dedicated input/output first in/first out module for a field programmable gate array

1. A field programmable gate array architecture having a plurality of input/output pads comprising:

a routing interconnect architecture programmably coupling a plurality of logic clusters, a plurality of input/output buffers and a plurality of input/output clusters; and

a plurality of dedicated input/output first-in/first-out memory blocks programmably coupled between said plurality of input/output buffers and said plurality of input/output clusters.

2. The field programmable gate array architecture of claim 1 , further comprising:

at least one input/output block controller programmably coupled to said plurality of dedicated input/output first-in/first-out memory blocks.

3. The field programmable gate array architecture of claim 2 , wherein said at least one input/output block controller further comprises:

a dedicated FIFO flag logic block coupled to said plurality of input/output clusters; and

an input/output FIFO block controller cluster programmably coupled to said dedicated FIFO flag logic block.

4. The field programmable gate array architecture of claim 3 , further comprising:

a plurality of logic components coupled to said plurality of input/output first-in/first-out memory blocks, wherein signals are transmitted and received from said at least one input/output block controller and said plurality of logic components;

wherein said input/output block controller further comprises:

an interconnect architecture coupling said plurality of logic components, at least one transmitter, at least one receiver, and at least one buffer.

5. The field programmable gate array architecture of claim 1 , wherein said dedicated input/output first-in/first-out memory blocks further comprises:

a plurality of input/output clusters coupled to at least one of the plurality of input/output pads, said plurality of input/output clusters comprising:

a plurality of input/output modules having a first-in/first-out memory coupled to said input/output pad and having a plurality of registers coupled to said first-in/first-out memory blocks; and

an interconnect architecture coupling together said input/output modules, at least one transmitter, at least one receiver and said plurality of input/output buffers.

6. A field programmable gate array having a plurality of input/output pads and dedicated input/output first-in/first-out memory, said dedicated input/output first-in/first-out memory comprising:

a plurality of input/output clusters coupled to said plurality of input/output pads, said plurality of input/output clusters comprising:

a plurality of input/output modules having a first-in/first-out memory coupled to said input/output pad and having a plurality of registers coupled to said first-in/first-out memory;

an interconnect architecture coupling said plurality of input/output modules, at least one transmitter, at least one receiver and at least one buffer; and

a plurality of input/output block controllers coupled to said plurality of input/output clusters.

7. The dedicated input/output first-in/first-out memory of claim 6 , wherein said plurality of input/output modules are coupled to said plurality of input/output pads through input and output buffers.

8. The dedicated input/output first-in/first-out memory of claim 6 , wherein said plurality of block controllers further comprise:

a random access memory block programmably coupled to said plurality of input/output clusters; and

an input/output block controller cluster coupled to said random access memory block.

9. The dedicated input/output first-in/first-out memory of claim 8 , further comprising:

a plurality of logic components coupled to said random access memory block, wherein signals are transmitted and received between said random access memory block and said plurality of input/output clusters.

10. The dedicated input/output first-in/first-out memory of claim 9 , wherein said plurality of logic components further comprise:

an interconnect architecture coupling together said plurality of logic components, at least one transmitter, at least one receiver, and at least one buffer.

11. A method of forming a dedicated input/output first-in/first-out memory in a field programmable gate array having a plurality of input/output pads comprising:

programmably coupling a plurality of logic clusters, a plurality of input/output buffers and a plurality of input/output clusters with a routing interconnect architecture; and

coupling a plurality of dedicated input/output first-in/first-out memory blocks between said plurality of input/output buffers and said plurality of input/output clusters.

12. The method of claim 11 , further comprising:

programmably coupling at least one input/output block controller to said plurality of dedicated input/output first-in/first-out memory blocks.

13. The method of claim 12 , wherein said plurality of block controllers further comprise:

a dedicated FIFO flag logic block coupled to said plurality of input/output clusters; and

an input/output FIFO block controller cluster programmably coupled to said dedicated FIFO flag logic block.

14. The method of claim 11 , wherein said plurality of dedicated input/output first-in/first-out memory blocks further comprise a plurality of input/output clusters coupled to the plurality of input/output pads, said plurality of input/output clusters comprising:

a plurality of input/output modules having a first-in/first-out memory coupled to said plurality of input/output pads and having a plurality of registers coupled to said first-in/first-out memory; and

an interconnect architecture coupling said input/output modules, at least one transmitter, at least one receiver and at least one buffer.

15. The method of claim 14 , wherein said plurality of input/output block controller cluster further comprises:

a plurality of logic components coupled to said plurality of dedicated input/output first-in/first-out memory blocks, wherein signals are transmitted and received between said plurality of first-in/first-out block controllers and said plurality of input/output clusters; and

an interconnect architecture coupling said plurality of logic components, at least one transmitter, at least one receiver, and at least one buffer.

16. A method of forming a first-in/first-out memory in a field programmable gate array having a plurality of input/output pads and dedicated input/output first-in/first-out memory blocks, said method comprising:

coupling a plurality of input/output clusters to said plurality of input/output pads, said plurality of input/output clusters comprising:

a plurality of input/output modules having a first-in/first-out memory coupled to said plurality of input/output pads, and a plurality of registers coupled to said first-in/first-out memory; and

an interconnect architecture coupling said plurality of input/output modules, at least one transmitter, at least one receiver and at least one buffer; and

coupling a plurality of input/output block controllers to said plurality of input/output clusters.

17. The method of claim 16 , wherein said plurality of input/out modules are coupled to said plurality of input/output pads through input and output buffers.

18. The method of claim 16 , wherein said plurality of first-in/first-out block controllers further comprise:

a first-in/first-out memory block programmably coupled to said plurality of input/output clusters; and

an input/output block controller cluster coupled to said first-in/first-out memory blocks.

19. The method of claim 18 , wherein said input/output block controller cluster comprises a plurality of logic components coupled to said first-in/first out memory block, wherein signals are transmitted and received between said first-in/first out memory block and said input/output block controller cluster.

20. The method of claim 19 , wherein said plurality of logic components further comprise:

an interconnect architecture coupling said logic components, at least one transmitter, at least one receiver, and at least one buffer.