Semiconductor power device having a diamond shaped metal interconnect scheme
View Patent ↗A transistor ( 10 ) is formed as a matrix of transistor cells ( 13 ) that have drain metal strips ( 50 ) for contacting drains ( 15 ) of the transistor cells and source metal strips ( 55 ) for contacting sources ( 35 ) of the transistor cells. An interconnect layer ( 1030 ) overlying the matrix of transistor cells has first portions ( 201 ) that contact one the drain metal strips with first and second vias ( 79 ) and second portions ( 101 ) that contact one of the source metal strips with third and fourth vias ( 78 ).
1. A semiconductor device comprising:
a matrix of transistor cells including drain metal strips for contacting drains of the transistor cells and source metal strips for contacting sources of the transistor cells; and
an interconnect layer overlying the matrix of transistor cells and having first and second drain portions, each contacting one of the drain metal strips with multiple vias, and first and second source portions, each contacting one of the source metal strips with multiple vias.
2. The device of claim 1 , wherein the multiple vias contacting each of the first and second drain portions are generally parallel to a line formed by the drain metal strips.
3. The device of claim 2 , wherein the first and second drain portions and the first and second source portions are formed having a generally diamond shape.
4. The device of claim 3 , wherein the first and second drain portions are adjacent to at least four source portions.
5. The device of claim 1 , wherein the matrix of transistor cells includes a matrix of mesh gate LDMOS transistor cells.
6. The device of claim 1 wherein a first drain metal strip is formed between first and second source metal strips and a third source metal strip is formed between second and third drain metal strips.
7. The device of claim 1 , wherein the interconnect layer includes eight source portions and eight drain portions.
8. The device of claim 1 , wherein the source and drain metal strips are formed of a metal including aluminum.
9. The device of claim 8 , wherein the interconnect layer is formed of aluminum or aluminum alloy.
10. The device of claim 1 , further comprising:
a first set of bumps formed on the first and second source portions of the interconnect layer for externally connecting to the sources of the transistor cells; and
a second set of bumps formed on the first and second drain portions of the interconnect layer for externally connecting to the drains of the transistor cells.
11. The device of claim 1 , further comprising a dielectric material separating the interconnect layer and the source and drain metal strips.
12. The device of claim 11 , further comprising a package for housing the matrix of transistor cells and the interconnect layer.
13. A gate mesh LDMOS device comprising:
an array of transistor cells including drain metal strips for contacting drains of the transistor cells and source metal strips for contacting sources of the transistor cells;
an interconnect layer overlying the array of transistor cells and having first generally diamond shaped portions, each first generally diamond shaped portion having multiple vias for contacting one of the drain metal strips, and second generally diamond shaped portions, each second generally diamond shaped portion having multiple vias for contacting one of the source metal strips.
14. The gate mesh LDMOS device of claim 13 , wherein the first and second generally diamond shaped portions are formed in a generally checkerboard array.
15. The gate mesh LDMOS device of claim 14 , wherein the second generally diamond shaped portions are arranged to alternate with the first generally diamond shaped portions.
16. The gate mesh LDMOS device of claim 15 , wherein the first and second generally diamond shaped portions contact all of the drain and source metal strips.
17. The gate mesh LDMOS device of claim 16 , wherein the drain and source metal strips are arranged in alternating rows to electrically contact alternating rows of drains and sources.
18. The gate mesh LDMOS device of claim 17 , further comprising:
a dielectric layer separating the first and second generally diamond shaped portions; and
a solder bump formed on each of the first and second generally diamond shaped portions for electrically contacting a circuit board trace or leadframe.
19. A semiconductor device comprising:
a substrate formed having a plurality of transistor cells formed in first and second perpendicular directions;
a first metal layer having first regions contacting sources of the transistor cells in the first perpendicular direction and second regions contacting drains of the transistor cells in the first perpendicular direction; and
a second metal layer formed over the first metal layer and having first generally diamond shaped portions coupled to a plurality of source contacts in first and second perpendicular directions and second generally diamond shaped portions for contacting the plurality of drain contacts in first and second perpendicular directions.
20. The semiconductor device of claim 19 , wherein the first and second portions of the first metal layer are formed of multiple parallel metal strips, alternating between contacting drains and sources.